MT8880C Mitel Networks Corporation, MT8880C Datasheet - Page 2

• Manufacturer Part Number: MT8880C
• Description: Integrated DTMFTransceiver
• Manufacturer: Mitel Networks Corporation

MT8880C/MT8880C-1
Pin Description
4-34
14-
20 24 28
10 12 14
11 13 15
12 14 17
13 15 18 IRQ/
17
18 22 26
19 23 27 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than V
20 24 28
1
2
3
4
5
6
7
8
9
Pin #
TONE
OSC1
OSC2
18-
10 12 TONE Tone output (DTMF or single tone).
21
VRef
11 13
8,9
16,
VSS
17
R/W
1
2
3
4
5
6
7
20 PIN CERDIP/PLASTIC DIP/SOIC
IN+
GS
CS
IN-
19-
3,5,
22
10,
16,
23-
11,
25
1
2
4
6
7
8 OSC1 DTMF clock/oscillator input.
9 OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the
10
1
2
3
4
5
6
7
8
9
D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS = 1 or
Name
V
R/W Read/Write input. Controls the direction of data transfer to and from the MPU and the
RS0 Register Select input. See register decode table. TTL compatible.
V
V
IN+ Non-inverting op-amp input.
ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid
GS Gain Select. Gives access to output of front end differential amplifier for connection of
CS
CP
NC No Connection.
IN-
Ref
SS
DD
2
Inverting op-amp input.
feedback resistor.
Reference Voltage output, nominally V
Ground input (0V).
internal oscillator circuit. Leave open circuit when OSC1 is clock input.
transceiver registers. TTL compatible.
Chip Select, TTL input (CS=0 to select the chip).
System Clock input. TTL compatible. N.B.
device is not being accessed.
Interrupt Request to MPU (open drain output). Also, when call progress (CP) mode has
been selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal
representative of the input signal applied at the input op-amp. The input signal must be within
the bandwidth limits of the call progress filter. See Figure 8.
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to
a logic low.
causes the device to register the detected tone pair and update the output latch. A voltage
less than V
external steering time-constant; its state is a function of ESt and the voltage on St.
Positive power supply input (+5V typical).
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
RS0
2
TSt
frees the device to accept a new tone pair. The GT output acts to reset the
OSC1
OSC2
TONE
VRef
VSS
R/W
IN+
GS
NC
NC
IN-
CS
ISO
Figure 2 - Pin Connections
10
11
12
1
2
3
4
5
6
7
8
9
24 PIN SSOP
2
-CMOS
24
23
22
21
20
19
18
17
16
15
14
13
DD
Description
/2 is used to bias inputs at mid-rail (see Fig. 13).
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
RS0
2
2 clock input need not be active when the
OSC1
OSC2
VRef
VSS
NC
NC
NC
5
6
7
8
9
10
11
28 PIN PLCC
TSt
detected at St
25
24
23
22
21
20
19
2 is low.
NC
NC
NC
D3
D2
D1
D0