MT8885 Mitel Networks Corporation, MT8885 Datasheet - Page 2

• Manufacturer Part Number: MT8885
• Description: Integrated DTMFTransceiver with Power Down & Adaptive Micro Interface
• Manufacturer: Mitel Networks Corporation

MT8885
4-52
Pin Description
14-
24
10
12
13
14
15
16
17
18
19
20
11
1
2
3
4
5
6
7
Pin #
18-
28
12
13 R/W(WR) (Motorola) Read/Write or (Intel) Write microprocessor input. CMOS compatible.
14
15
17
18
19
21
22
23
24
R/W/WR
1
2
4
6
7
8
9
OSC1
OSC2
TONE
VRef
VSS
IN+
GS
NC
NC
IN-
CS
DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is only
IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes
PWDN
D0-D3
TONE
Name
OSC1
OSC2
St/GT
RS0
V
IN+
V
ESt
V
IN-
GS
CS
Ref
DD
SS
24 PIN DIP/SSOP
10
11
12
1
2
3
4
5
6
7
8
9
Non-inverting op-amp input.
Inverting op-amp input.
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage output (V
Ground (0V).
Oscillator input. This pin can also be driven directly by an external clock.
Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes
the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
Output from internal DTMF transmitter.
Chip Select input. This signal must be qualified externally by either address strobe (AS),
valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.
Register Select input. Refer to Table 3 for bit interpretation. CMOS compatible.
required when the device is being accessed. CMOS compatible.
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter, see
Figure 8.
Power Down (input). Active High. Powers down the device and inhibits the oscillator. IRQ
and TONE output are high impedance. Data bus is held in tri-state. This pin is internally
pulled down.
Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
(Intel). TTL compatible.
Early Steering output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
Steering Input/Guard Time output (bidirectional). A voltage greater than V
St causes the device to register the detected tone pair and update the output latch. A
voltage less than V
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
Positive power supply (5V typ.).
24
23
22
21
20
19
18
17
16
15
14
13
VDD
St/GT
ESt
D3
D2
D1
D0
NC
PWDN
IRQ/CP
DS/RD
RS0
TSt
frees the device to accept a new tone pair. The GT output acts to
Figure 2 - Pin Connections
DD
/2).
OSC1
OSC2
VRef
VSS
Description
NC
NC
NC
5
6
7
8
9
10
11
28 PIN PLCC
25
24
23
22
21
20
19
Advance Information
NC
D3
D2
D1
D0
NC
PWDN
TSt
detected at