MT8977 Mitel Networks Corporation, MT8977 Datasheet
MT8977
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MT8977 Summary of contents
Page 1
... T1 registered trademark of AT & T ISO-CMOS ST-BUS T1/ESF Framer Circuit (ACCUNET MT8977AC MT8977AE MT8977AP Description The MT8977 is a variant of the MT8976 framer, which has been enhanced to meet ACCUNET wander tolerance (138 UI). The MT8977 meets ESF and D3/D4 formats, and is compatible with SLC-96 systems. 2 Frame Elastic Buffer ...
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... MT8977 ISO-CMOS 1 TxA 28 VDD 2 TxB DSTo 26 F0i E1.5i 5 RxA 24 C1. RxB RxSF 7 RxD 22 TxSF 8 CSTi1 21 C2i 9 TxFDL 20 RxFDL 10 TxFDLClk 19 DSTi RxFDLClk 12 17 CSTi0 CSTo 13 16 E8Ko XSt 14 VSS 15 XCtl 28 PIN CERDIP/PDIP Pin Description Pin # Name DIP PLCC 1 2 TxA Transmit A Output ...
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... RxD, RxA and RxB F0i Frame Pulse Input. This is the frame synchronization signal which defines the beginning of the 32 channel ST-BUS frame Internal Connection. Tied Positive Power Supply Input. +5V 5%. DD ISO-CMOS Description for normal operation SS . MT8977 4-101 ...
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... MT8977 ISO-CMOS Functional Timing Diagrams C2i DSTi DSTo CSTi0/CSTi1 CSTo E1. INT DATA DS1 AMI LINE SIGNAL RxA RxB RxD E8Ko C1.5i INT DATA TxA TxB DS1 AMI LINE SIGNAL 4-102 125 Sec • • • • ...
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... Preliminary Information MT8977 ISO-CMOS 4-103 ...
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... ST-BUS stream, and one of these 64 kbit/s channels is known as an ST-BUS channel. The system side of the MT8977 is made up of ST- BUS inputs and outputs, i.e. control inputs and outputs (CSTi/o) and data inputs and outputs (DSTi/o). These signals are functionally represented in Figure 3 ...
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... The combination of bits 5 and 6 in Master Control Word 1 allow one of three zero code suppression schemes to be selected. The three choices are: none, binary 8 zero suppression (B8ZS), or jammed bit (bit 7 forced high). No zero code suppression MT8977 ISO-CMOS . th frame is enabled. As long as the serial ...
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... The MT8977 also has a per channel loopback mode. See Table 6 and the following section for more information. Per Channel Control Features In addition to the two master control words in CSTi0 there are also 24 Per Channel Control Words ...
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... It will be reset when the device resynchronizes. mimic bit, the terminal framing error bit and the CRC error counter can be used separately or together to The decide if the receiver should be forced to reframe. MT8977 ISO-CMOS Even The CSTo serial stream contains The Master error ...
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... MT8977 ISO-CMOS Frame † Resynchronization Concentrator ...
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... For example, if the channel count in the phase status word is seen to increase over time, the feedback applied to the VCO is used to decrease the system clock frequency until a reversal in the trend is observed. Description Description MT8977 ISO-CMOS The rising edge of E8Ko 4-109 ...
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... Word Table 11. Per Channel Status Word Output on CSTo The elastic buffer in the MT8977 permits the device to handle 26 ST-BUS channels or 156 UI of jitter/ wander (see description of elastic buffer in the next section). In order to prevent slips from occurring, the frequency corrections would have to be implemented such that the deviation in the phase status word is limited to 26 channels peak-to-peak ...
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... Clock and Framing Signals The MT8977 requires one 2.048 MHz clock (C2i) and an 8 kHz framing signal for the ST-BUS side. Figure 2 illustrates the relationship between the two signals. The framing signal is used to delimit individual 32 channel ST-BUS frames ...
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... MT8977 ISO-CMOS Write Pointer 386 Bit 47 CH Elastic Store 34 CH Figure 8 - Elastic Buffer Functional Diagram (156 UI Wander Tolerance) decrease over time. When this delay approaches the minimum two channel threshold, the buffer will perform a controlled slip, which will reset the internal ST-BUS read pointers so that there is exactly 34 channels delay between the two pointers ...
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... Master Control Word 2. This bit changes the out of frame conditions for the maintenance state. MT8977 ISO-CMOS Forced Reframe Maintenance Valid Candidate ...
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... RxD. uncommitted nand gate in the MT8940/41 can be used for this purpose. The MT8977 can be interfaced to a high speed parallel bus microprocessor using the MT8920B Parallel Access Circuit (STPA). Figure 11 Preliminary Information ...
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... Preliminary Information shows the MT8977 interfaced to a parallel bus structure using two STPA‘s operating in modes 1 and 2. The first STPA operating in mode 2 (MMS=0, MS1=1, 24/32=0), routes data information between the parallel telecom bus and the T1 or CEPT link via DSTi and DSTo. The second ...
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... A -A STi0 0 5 STo1 CS SIGNALLING and DS LINK R/W CONTROL DTACK C4i BUS IRQ F0i lACK MMS +5V Figure 12 - Using the MT8977 in a Parallel Bus Environment 4-116 MT8977 Tx DSTi TxA Line DSTo TxB Driver CSTi0 CSTo CSTi1 • Rx • F0i RxA Line • C2i ...
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... 4 1 † - Capacitance ‡ Sym Min Typ Max MT8977 ISO-CMOS Min Max Units -0 -0 -55 125 C 800 mW ) unless otherwise stated. ss Units Test Conditions For 400 mV noise margin V ...
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... MT8977 ISO-CMOS AC Electrical Characteristics Characteristics 1 C2i Clock Period 2 C2i Clock Width High or Low 3 Frame Pulse Setup Time 4 Frame Pulse Hold Time 5 Frame Pulse Width 6 RxSF Output Delay 7 TxSF Hold Time 8 TxSF Setup Time † Timing is over recommended temperature & power supply voltages ‡ ...
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... Sym Min Typ Max t 125 SOD t 15 SIS t 50 SIH Bit Cell Boundaries t SOD t t SIS SIH Figure 16 - ST-BUS Stream Timing MT8977 ISO-CMOS Units Test Conditions 648 ns PEC BIT CELL t WEC t WEC Units Test Conditions ns 150 pF load SOD ...
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... MT8977 ISO-CMOS AC Electrical Characteristics Parameters 1 External Control Delay 2 External Status Setup Time 3 External Status Hold Time 4 8 kHz Output Delay 5 8 kHz Output Low Width 6 8 kHz Output High Width 7 8 kHz Rise Time 8 8 kHz Fall Time † Timing is over recommended temperature & power supply voltage ranges. ...
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... PC1.5 t 250 324 WC1.5 Bit Cell t PC1.5 t WC1 TSD Bit Cell t t RSS RSH t t RDH RDS MT8977 ISO-CMOS Units Test Conditions 150 ns 150 pF Load 30 ns 150 pF Load See Note 1 ns See Note 1 800 648 ns PC1.5 TSD ...
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... MT8977 ISO-CMOS AC Electrical Characteristics Parameters 1 Transmit FDL Setup Time 2 Transmit FDL Hold Time 3 Receive FDL Output Delay 4 Receive FDL Clock Delay 5 Transmit FDL Clock Delay † Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are and are for design aid only; not guaranteed and not subject to production testing ...
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... CHANNEL 30 (8/2.048) s BIT 4 BIT 5 BIT 3 BIT 2 BIT 6 125 s CHANNEL • • • • • • 23 (8/1.544) s BIT 3 BIT 4 BIT 5 BIT 6 BIT 2 Figure 25 - DS1 Link Frame Format MT8977 ISO-CMOS CHANNEL CHANNEL 31 0 BIT 1 BIT 0 CHANNEL CHANNEL S Bit 24 1 BIT 7 BIT 8 4-123 ...
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... MT8977 ISO-CMOS Appendix Control and Status Register Summary 7 6 Debounce TSPZCS B8ZS 1 Disabled 1 Disabled 1 B8ZS 0 Enabled 0 Enabled 0 Jammed Bit Master Control Word 1 (Channel 15, CSTi0) RMLOOP DGLOOP ALL 1’s 1 Enabled 1 Enabled 1 Enabled 0 Disabled 0 Disabled 0 Disabled Master Control Word 2 (Channel 31, CSTi0) UNUSED - KEEP AT 0 ...