PM102ZY3 AZ Displays, Inc, PM102ZY3 Datasheet - Page 9

• Manufacturer Part Number: PM102ZY3
• Description: Color Tft Lcd Module
• Manufacturer: AZ Displays, Inc

Note 5-1: Gate off voltage, VEE=-5.6V
Note 5-2: Gate on voltage, VGG=17V
Note 5-3: Select up or down shift
Note 5-4: Gate driver shift clock
Note 5-5: When OE is connected to high “1”, the driver outputs are disabled (Gate output = VEE). Under
Note 5-6: Select left or right shift
Note 5-7: Latch the polarity of outputs and switch the new data to outputs. At the rising edge (LD), latch
Note 5-9: Polarity selector for dot-inversion control. Available at the rising edge of LD.
Note 5-10: Clock signal. When RSDS input mode, CLK is used as CLKP input pin.
Note 5-11: The RSDS clock input pairs generate the internal shift clock through the comparison between
Note 5-12: TTL/RSDS=H: RSDS data input
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Note 5-8: Control whether the Data R0~G5 are inverted or not. (PVI suggests connecting to GND)
U/D
this condition, the operation of registers will not be affected.
R/L
the “POL” signal to control the polarity of the outputs.
When “REV=1”, these data will be inverted.
EX: “00”→”3F”, “07”→”38”, “15”→”2A”
When POL=1: Even outputs range from V1~V7, and Odd outputs range from V8~V14; When
POL=0: Even outputs range from V8~V14, and Odd outputs range from V1~V7.
CLKP and CLKN. When TTL mode, connect to GND.
TTL/RSDS=L or open: TTL data input
1
0
1
0
STVU
DIO1
Input
Input
Hi-Z
Hi-Z
STVD
DIO2
Input
Input
Hi-Z
Hi-Z
Left to Right
Right to Left
Down to Up
Up to Down
Shift
Shift
PM102ZY3