P123-09H PhaseLink Corp., P123-09H Datasheet - Page 3

• Manufacturer Part Number: P123-09H
• Description: Low Skew Zero Delay Buffer
• Manufacturer: PhaseLink Corp.

LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
- Long trace = Transmission Line. Without proper termi-
- Design long traces as “striplines” or “microstrips” with
- Match trace at one side to avoid reflections bouncing
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 4/9/08 Page 3
ringing!
nation this will cause reflections ( looks like ringing ).
defined impedance.
back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible
- Addition of a ferrite bead in series with VDD can
- Value of decoupling capacitor is frequency de-
to the VDD pin(s) to limit noise from the power
supply
help prevent noise from other board sources
pendant. Typical values to use are 0.1F for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
Low Skew Zero Delay Buffer
(Preliminary)