P123-08H PhaseLink Corp., P123-08H Datasheet - Page 2

• Manufacturer Part Number: P123-08H
• Description: 3.3v Zero Delay Buffer
• Manufacturer: PhaseLink Corp.

PIN DESCRIPTION
SELECT INPUT DECODING
AVAILABLE CONFIGURATIONS
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak pull-up on these inputs.
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 7/19/07 Page 2
Pin
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
S2
5: Output is phase indeterminant (0° or 180° from input clock). If phase integrity is required, use PL123-082.
0
0
1
1
4: Outputs inverted on PL123-082 and -083 in bypass mode (S2=1, S1=0).
PL123-08H
PL123-082
PL123-082
PL123-083
PL123-083
PL123-08
Device
CLKA1
CLKA2
CLKB1
CLKB2
CLKB3
CLKB4
CLKA3
CLKA4
Name
REF
VDD
GND
GND
VDD
S2
S1
FBK
[3]
[3]
[1]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
S1
0
1
0
1
Type
O
O
O
O
O
O
O
O
P
P
P
P
I
I
I
I
Bank A or Bank B
Bank A or Bank B
Feedback From
Bank A
Bank B
Bank A
Bank B
Input reference frequency
Clock output, Bank A
Clock output, Bank A
3.3V supply
Ground
Clock output, Bank B
Clock output, Bank B
Select input, bit 2
Select input, bit 1
Clock output, Bank B
Clock output, Bank B
Ground
Clock output, Bank A
Clock output, Bank A
PLL feedback input
3.3V supply
CLK A1–A4
Three-State
Driven
Driven
Driven
[4]
Bank A Frequency
CLK B1–B4
Three-State
Three-State
2 X Reference
2 X Reference
4 X Reference
Driven
Reference
Reference
Reference
Driven
[4]
Description
3.3V Zero Delay Buffer
(Preliminary)
Output Source
Reference or Inverted Reference
Reference
PLL
PLL
PLL
Bank B Frequency
2 X Reference
Reference / 2
Reference
Reference
Reference
PL123-08
PLL Shutdown
N
N
Y
Y
[5]