SST39LF160 Silicon Storage Technology, SST39LF160 Datasheet - Page 3

• Manufacturer Part Number: SST39LF160
• Description: (SST39VF160 / SST39LF160) 16 Mbit (x16) Multi-Purpose Flash
• Manufacturer: Silicon Storage Technology

16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
Data# Polling (DQ
When the SST39LF/VF160 are in the internal Program
operation, any attempt to read DQ
plement of the true data. Once the Program operation is
completed, DQ
ready for the next operation. During internal Erase opera-
tion, any attempt to read DQ
internal Erase operation is completed, DQ
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the ris-
ing edge of sixth WE# (or CE#) pulse. See Figure 5 for
Data# Polling timing diagram and Figure 16 for a flowchart.
Toggle Bit (DQ
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
stop toggling. The device is then ready for the next opera-
tion. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 6 for Toggle
Bit timing diagram and Figure 16 for a flowchart.
Data Protection
The SST39LF/VF160 provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
©2001 Silicon Storage Technology, Inc.
7
will produce true data. The device is then
6
)
7
)
7
6
will produce a ‘0’. Once the
will produce alternating 1s
7
will produce the com-
7
will produce a
6
bit will
3
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V
inhibited when V
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39LF/VF160 provide the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table
4 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
device to read mode within T
can be V
mand sequence.
DD
Power Up/Down Detection: The Write operation is
IL
or V
IH
DD
, but no other value, during any SDP com-
is less than 1.5V.
RC
. The contents of DQ
S71145-02-000 6/01
15
-DQ
399
8