MC10EP33 ON Semiconductor, MC10EP33 Datasheet

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MC10EP33

Manufacturer Part Number
MC10EP33
Description
3.3V 5VECL / 4 Divider
Manufacturer
ON Semiconductor
Datasheet

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MC10EP33
B
inputs and the V BB allow a differential, single–ended or AC coupled
interface to the device. If used, the V BB output should be bypassed to
ground with a 0.01 F capacitor.
Upon power–up, the internal flip–flops will attain a random state; the
reset allows for the synchronization of multiple EP33’s in a system.
December, 1999 – Rev. 1
The MC10EP33 is an integrated
The reset pin is asynchronous and is asserted on the rising edge.
Oxygen Index 28 to 34
320ps Propagation Delay
3 GHz Typical Toggle Frequency
PECL mode: 3.0V to 5.5V V CC with V EE = 0V
ECL mode: 0V V CC with V EE = –3.0V to –5.5V
Internal Input Resistors: Pulldown on D, D
Q Output will default LOW with inputs open or at V EE
ESD Protection: >4KV HBM, >200V MM
V BB Output
New Differential Input Common Mode Range
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack
Flammability Rating: UL–94 code V–0 @ 1/8”,
Transistor Count = 91 devices
Semiconductor Components Industries, LLC, 1999
4 Divider
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
RESET
V BB
CLK
CLK
1
2
3
4
B
4 divider. The differential clock
B
R
4
8
7
6
5
V CC
Q
Q
V EE
1
*For additional information, see Application Note
MC10EP33D
MC10EP33DR2
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 4 Function
AND8002/D
CLK
CLK, CLK
X
Z
Reset
8
1
V BB
Q, Q
V CC
V EE
PIN
Device
HEP33
ALYW
CLK
ORDERING INFORMATION
X
Z
MARKING DIAGRAM
PIN DESCRIPTION
http://onsemi.com
8
TRUTH TABLE
RESET
ECL Asynchronous Reset
Reference Voltage Output
Package
CASE 751
D SUFFIX
SOIC
SOIC
Z
L
SO–8
Negative, 0 Supply
ECL Data Outputs
ECL Clock Inputs
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
Positive Supply
Publication Order Number:
1
FUNCTION
2500 Tape & Reel
Q
L
F
98 Units/Rail
Shipping
MC10EP33/D
Q
H
F

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MC10EP33 Summary of contents

Page 1

... MC10EP33 B 4 Divider B The MC10EP33 is an integrated 4 divider. The differential clock inputs and the V BB allow a differential, single–ended or AC coupled interface to the device. If used, the V BB output should be bypassed to ground with a 0.01 F capacitor. The reset pin is asynchronous and is asserted on the rising edge. ...

Page 2

... JC T sol Solder Temperature (< Seconds: 245 C desired) * Maximum Ratings are those values beyond which damage to the device may occur. { Use for inputs of same package only. CLK RESET Q MC10EP33 Parameter Continuous Surge { Still Air 500lfpm t RR Figure 2. Timing Diagram http://onsemi.com ...

Page 3

... 3.3V 0V, all other pins floating. 6. All loading with 50 ohms –2.0 volts IHCMR min varies 1:1 with max varies 1:1 with Input and output parameters vary 1:1 with MC10EP33 – Min Typ ...

Page 4

... F max guaranteed for functionality only and V OH levels are guaranteed at DC only. 14. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. MC10EP33 0.5V 0V) (Note 12.) –40 C ...

Page 5

... A C SEATING PLANE 0. 0. MC10EP33 SO–8 D SUFFIX CASE 751–06 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME C Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION ...

Page 6

... Notes MC10EP33 http://onsemi.com 6 ...

Page 7

... Notes MC10EP33 http://onsemi.com 7 ...

Page 8

... Email: ONlit–asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549 Phone: 81–3–5487–8345 Email: r14153@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC10EP33/D ...

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