NCV8851B ON Semiconductor, NCV8851B Datasheet - Page 10

• Manufacturer Part Number: NCV8851B
• Description: Automotive Grade Synchronous Buck Controller
• Manufacturer: ON Semiconductor

threshold when the part is enabled and the LDO output has
risen. After an initial delay to assure a clean start−up,
switching begins, the output initially rises quickly and then
rises monotonically. The duty cycle is gradually increased
until V
cycle is reached.
Normal Shutdown Behavior and Sleep Mode
because the input supply drops below the UVLO threshold,
the part enters TSD or the part is disabled. When disabled,
the part enters sleep mode.
discharges, causing switching to stop, the internal soft−start
capacitor to discharge and GH and GL to go low. The switch
node enters a high impedance state and the output inductor
and capacitors discharge through the load. The supply
current reduces to the sleep mode quiescent current.
Internal Linear Regulator (LDO)
regulator (LDO) internally connected to drive the low−side
gate. The 6V
V
is used from 6V
the internal rails.
placed from 6V
the BST pin for the high−side floating gate driver. This
ensures that the voltage on BST is about 6V
V
enough to enhance the high−side MOSFET. The BST
capacitor supplies the charge used by the gate driver to
charge up the input capacitance of the high−side MOSFET,
and is typically chosen to be at least a decade larger than this
capacitance. A 0.1 mF BST capacitor is recommended.
IN_IC
SW
This sequence begins once V
Normal shutdown occurs when the IC stops switching
In sleep mode, the LDO turns off and its output capacitor
The NCV8851B has an onboard low−dropout linear
A capacitor is placed from V
, less a diode drop, yielding a gate drive voltage high
OUT
pin to power the internal rails. Typically, a RC filter
has reached its set point or until maximum duty
OUT
OUT
OUT
pin should be externally connected to the
to BST to create a bootstrap supply on
to V
IN_IC
PWM
Output
to further decrease noise on
IN_IC
SW
to BST and a diode is
MainFault
surpasses its UVLO
Main
Fault
Figure 23. Gate Driver Block Diagram
OUT
higher than
GH to GL
GL to GH
Delay
Delay
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NCV8851B
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Threshold
Threshold
diode to the BST pin, charging the BST capacitor during
off−time to generate a voltage for the high−side driver.
When the part is enabled and V
regulated value, the LDO is in dropout and it tracks V
LDO regulates its output once V
point plus the dropout voltage.
6V
condition on the 6V
current limit and internal thermal shutdown (TSD) circuitry
which disables all outputs. A normal soft−start will occur
when the die temperature falls below the TSD threshold.
Drivers
external
NCV8851B to address high−power, as well as low−power
conversion requirements. The gate drivers also include
adaptive non−overlap circuitry. The non−overlap circuitry
increases efficiency, which minimizes power dissipation, by
minimizing the body diode conduction time, while
protecting against cross−conduction (shoot−through) of the
MOSFETs. A detailed block diagram of the non−overlap
and gate drive circuitry used in the chip and related external
components is shown in Figure 23.
low−side MOSFET is on, pulling V
NCV8851B has a minimum off−time. This also means that
the BST capacitor cannot be arbitrarily large, since 6V
needs to be able to charge it up during this minimum
off−time so the high−side gate driver doesn’t run out of
headroom. 6V
capacitor and also the low−side driver, so the LDO capacitor
must be sufficiently larger than the BST capacitor. A 1 mF
LDO capacitor is recommended.
V
GL
The 6V
An external bypass capacitor must be connected from
The NCV8851B includes 1.5 A gate drivers to switch
Since the BST capacitor only recharges when the
SW
OUT
to ground. A short to ground or overcurrent
OUT
N−Channel
pin should be externally connected through a
OUT
6V
PGND
needs to supply charge both to the BST
BST
V
GL
GH
OUT
SW
OUT
pin will be mitigated by the LDO
MOSFETs.
IN
SW
IN
is above the output set
V
SW
is below the LDO
down to ground, the
This
allows
IN
. The
OUT
the
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