EMC6D102 SMSC Corporation, EMC6D102 Datasheet - Page 53

• Manufacturer Part Number: EMC6D102
• Description: Fan Control Device
• Manufacturer: SMSC Corporation

Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
SMSC EMC6D102
7.2.9
Register
Address
BIT
4-7
0
1
2
3
40h
Reserved
READY
START
OVRID
NAME
LOCK
Read/
Write
R/W
Further, application software may use the current stepping to implement work-arounds for bugs found
in a specific silicon stepping. This register is read only – a write to this register has no effect.
Register 40h: Ready/Lock/Start Monitoring
Setting the Lock bit makes the Lock and Start bits read-only.
R/W
R/W
R/W
R/W
Ready/Lock/Start
R
R
Register Name
DEFAULT
0
0
0
0
0
When software writes a 1 to this bit, the EMC6D102 en-
ables monitoring and PWM output control functions based
on the limit and parameter registers. Before this bit is set,
the part does not update register values. Whenever this bit
is set to 0, the monitoring and PWM output control func-
tions are based on the default limits and parameters, regard-
less of the current values in the limit and parameter
registers. The EMC6D102 preserves the values currently
stored in the limit and parameter registers when this bit is
set or cleared. This bit becomes read only when the Lock bit
is set.
Note:
It is expected that all limit and parameter registers will be
set by BIOS or application software prior to setting this bit
because these registers cannot be written once the start bit
is set.
Setting this bit to 1 locks specified limit and parameter reg-
isters. Once this bit is set, limit and parameter registers be-
come read only and will remain locked until the device is
powered off. This register bit becomes read only once it is
set.
The EMC6D102 sets this bit automatically after the part is
fully powered up, has completed the power-up-reset pro-
cess, and after all A/D converters are functioning (all bias
conditions for the A/Ds have stabilized and the A/Ds are in
operational mode). (Always reads back ‘1’.)
If this bit is set to 1, all PWM outputs go to 100% duty cycle
regardless of whether or not the lock bit is set.
Reserved.
(MSb)
Bit 7
RES
DATASHEET
Bit 6
When this bit is 0, all fans are on full 100% duty cycle, i.e.,
PWM pins are high for 255 clocks, low for 1 clock. When this
bit is 0, the part is not monitoring.
RES
53
Bit 5
RES
Bit 4
RES
DESCRIPTION
OVRID
Bit 3
READY
Bit 2
LOCK
Bit 1
Revision 0.4 (06-15-06)
START
(LSb)
Bit 0
Default
Value
00h