74HCT85DB,112 NXP Semiconductors, 74HCT85DB,112 Datasheet - Page 14
74HCT85DB,112
Manufacturer Part Number
74HCT85DB,112
Description
IC COMPARATOR MAGNITUDE 16SSOP
Manufacturer
NXP Semiconductors
Series
74HCTr
Type
Magnitude Comparatorr
Datasheets
1.74HCT4046ADB112.pdf
(19 pages)
2.74HCT4046ADB112.pdf
(23 pages)
3.74HC85D652.pdf
(9 pages)
Specifications of 74HCT85DB,112
Package / Case
16-SSOP
Number Of Bits
4
Delay Time - Propagation
26ns
Voltage - Supply
4.5 V ~ 5.5 V
Product
Digital Comparators
Input Bias Current (max)
0.008 mA
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Propagation Delay Time
44 ns
Current - Supply
-
Operating Temperature
-
Logic Family
HCT
Technology
CMOS
High Level Output Current
-4mA
Low Level Output Current
4mA
Output Function
A<B, A=B, A>B
Package Type
SSOP
Quiescent Current
8uA
Mounting
Surface Mount
Pin Count
16
Polarity
Non-Inverting
Abs. Propagation Delay Time
66ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Operating Temperature (max)
125C
Operating Temperature (min)
-40C
Operating Temperature Classification
Automotive
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Operating Temperature
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-2911-5
935190310112
935190310112
Philips Semiconductors
AC waveforms 74HCT (continued)
Test circuit for 74HCT
March 1988
handbook, full pagewidth
handbook, full pagewidth
HCMOS family characteristics
Switch position
Note
1. For open-drain N-channel outputs t
TEST
t
t
t
t
C
R
PZH
PZL
PHZ
PLZ
L
T
=
=
load capacitance including jig and probe capacitance
(see AC CHARACTERISTICS for values).
termination resistance should be equal to the output impedance Z
the pulse generator.
SWITCH
GND
V
GND
V
CC
CC
LOW-to-OFF
OFF-to-LOW
HIGH-to-OFF
OFF-to-HIGH
MGK566
OUTPUT
OUTPUT
OUTPUT
ENABLE
GENERATOR
PULSE
Fig.11 Propagation delays of 3-state outputs.
90%
Fig.12 Test circuit for 3-state outputs.
PLZ
t f
1.3 V
10%
and t
V I
t PLZ
enabled
outputs
t PHZ
PZL
R T
are applicable.
10%
D.U.T
V CC
90%
14
o
of
disabled
outputs
V O
C L
t r
t PZL
t PZH
R L = 1 k
50 pF
FAMILY SPECIFICATIONS
1.3 V
MGK563
1.3 V
outputs
enabled
V CC