MC14024B
7−Stage Ripple Counter
delays and high maximum clock rates. The Reset input has standard
noise immunity, however the Clock input has increased noise
immunity due to Hysteresis. The output of each counter stage is
buffered.
Features
•
•
•
•
•
•
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
either V
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2006
Symbol
V
I
The MC14024B is a 7−stage ripple counter with short propagation
in
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
Schottky TTL Load Over the Rated Temperature Range
in
Diode Protection on All Inputs
Output Transitions Occur on the Falling Edge of the Clock Pulse
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−power TTL Loads or One Low−power
Pin−for−Pin Replacement for CD4024B
Pb−Free Packages are Available
V
T
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
P
, V
, I
T
T
stg
DD
A
D
L
out
out
SS
or V
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation, per Package
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
DD
(DC or Transient)
(DC or Transient) per Pin
(Note 1)
(8−Second Soldering)
v (V
). Unused outputs must be left open.
in
Parameter
or V
(Voltages Referenced to V
out
) v V
DD
.
in
and V
−0.5 to V
SS
−0.5 to +18.0
−55 to +125
−65 to +150
out
)
Value
± 10
500
260
should be constrained
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
A
WL, L
YY, Y
WW, W
G
ORDERING INFORMATION
CASE 751A
SOEIAJ−14
CASE 646
CASE 965
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
P SUFFIX
D SUFFIX
F SUFFIX
PDIP−14
SOIC−14
Publication Order Number:
14
1
14
14
1
1
MC14024BCP
DIAGRAMS
AWLYYWWG
MARKING
MC14024B
AWLYWW
MC14024B/D
ALYWG
14024BG