MC14029B
Binary/Decade Up/Down
Counter
with MOS P−channel and N−channel enhancement mode devices in a
single monolithic structure. The counter consists of type D flip−flop
stages with a gating structure to provide toggle flip−flop capability.
The counter can be used in either Binary or BCD operation. This
complementary MOS counter finds primary use in up/down and
difference counting and frequency synthesizer applications where low
power dissipation and/or high noise immunity is desired. It is also
useful in A/D and D/A conversion and for magnitude and sign
generation.
Features
•
•
•
•
•
•
•
•
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
(e.g., either V
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2005
Symbol
V
I
The MC14029B Binary/Decade up/down counter is constructed
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level
of Clock
Schottky TTL Load Over the Rated Temperature Range
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Speed
Logic Edge−Clocked Design − Count Occurs on Positive Going Edge
Asynchronous Preset Enable Operation
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Pin for Pin Replacement for CD4029B
Pb−Free Packages are Available*
in
in
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
V
T
P
, V
, I
T
T
DD
stg
D
A
L
out
out
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation, per Package
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
SS
(DC or Transient)
(DC or Transient) per Pin
(Note 1)
(8−Second Soldering)
or V
v (V
DD
in
). Unused outputs must be left open.
Parameter
or V
(Voltages Referenced to V
out
) v V
DD
.
in
and V
−0.5 to V
−0.5 to +18.0
SS
−55 to +125
−65 to +150
out
)
Value
± 10
500
260
should be constrained
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
A
WL, L
YY, Y
WW, W
G
C
V
C
PE
Q3
Q0
P3
P0
out
SS
PIN ASSIGNMENT
in
CASE 751B
SOEIAJ−16
CASE 648
CASE 966
P SUFFIX
D SUFFIX
F SUFFIX
PDIP−16
SOIC−16
1
2
3
4
5
6
7
8
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
Publication Order Number:
16
15
14
13
12
10
11
9
16
1
16
16
1
1
V
CLK
Q2
P2
P1
Q1
U/D
B/D
DIAGRAMS
MC14029BCP
DD
AWLYYWWG
MARKING
MC14029B
AWLYWW
MC14029B/D
14029BG
ALYWG