TS2GDOM44V-S Transcend Information. Inc., TS2GDOM44V-S Datasheet - Page 17
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TS2GDOM44V-S
Manufacturer Part Number
TS2GDOM44V-S
Description
Transcend 44-pin Ide Flash Module
Manufacturer
Transcend Information. Inc.
Datasheet
1.TS2GDOM44V-S.pdf
(34 pages)
Sustaining an Ultra DMA Data-In Burst
is shown in below: Sustained Ultra DMA Data-In Burst Timing. The timing parameters are specified in
Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data
Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The device shall drive a data word onto D[15:00].
b) The device shall generate a DSTROBE edge to latch the new word no sooner than t
c) The device shall not change the state of D[15:00] until at least t
d) The device shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA data
Notes: D[15:00] and DSTROBE signals are shown at both the host and the device to emphasize that cable settling
the state of D[15:00]. The device shall generate a DSTROBE edge no more frequently than t
selected Ultra DMA mode. The device shall not generate two rising or two falling DSTROBE edges
more frequently than 2t
to latch the data.
burst is paused, whichever occurs first.
Transcend Information Inc.
time as well as cable propagation delay shall not allow the data signals to be considered stable at the host
until some time after they are driven by the device.
An Ultra DMA Data-In burst is sustained by following the steps lettered below. The timing diagram
T
T
T
r
r
r
a
a
a
n
n
n
s
s
s
c
c
T
c
T
T
e
e
e
S
S
S
n
n
n
1
1
1
d
d
d
2
2
2
cyc
8
8
8
4
4
4
M
M
M
for the selected Ultra DMA mode.
4
4
4
-
-
-
P
P
~
P
~
~
i
i
i
8
n
n
8
n
8
G
G
G
I
I
I
D
D
D
D
D
D
E
E
E
O
O
O
M
F
F
M
F
M
l
l
l
4
4
a
a
4
a
4
s
4
s
4
s
17
V
h
V
h
V
h
-
-
-
M
M
S
S
M
S
o
o
o
d
d
d
u
u
u
l
l
l
e
e
e
DVH
after generating a DSTROBE edge
DVS
after changing
CYC
for the
Ver 1.2