S12CPUV2 Motorola, S12CPUV2 Datasheet - Page 89
S12CPUV2
Manufacturer Part Number
S12CPUV2
Description
MC9S12DT128 Device User Guide V02.09
Manufacturer
Motorola
Datasheet
1.S12CPUV2.pdf
(138 pages)
- Current page: 89 of 138
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Section 21 Port Integration Module (PIM) Block Description
Consult the PIM_9DTB128 Block User Guide for information about the Port Integration Module.
Section 22 Voltage Regulator (VREG) Block Description
Consult the VREG Block User Guide for information about the dual output linear voltage regulator.
Section 23 Printed Circuit Board Layout Proposal
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
•
•
Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 – C6).
Central point of the ground star should be the VSSR pin.
Component
C11 / C
C10 / C
C9 / C
R2 / R
R3 / R
R1 / R
C1
C2
C3
C4
C5
C6
C7
C8
Q1
Table 23-1 Suggested External Component Values
S
DC
B
S
P
PLL loop filter cap
PLL loop filter cap
VDDPLL filter cap
PLL loop filter res
VDDA filter cap
VDDR filter cap
VDDX filter cap
VDD1 filter cap
VDD2 filter cap
OSC load cap
OSC load cap
DC cutoff cap
Purpose
Quartz
Colpitts mode only, if recommended by
X7R/tantalum
X7R/tantalum
ceramic X7R
ceramic X7R
ceramic X7R
ceramic X7R
See PLL Specification chapter
See PLL specification chapter
Type
MC9S12DT128 Device User Guide — V02.09
quartz manufacturer
Pierce mode only
100 … 220nF
100 … 220nF
>= 100nF
>= 100nF
Value
100nF
100nF
89
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