SL4029B System Logic Semiconductor, SL4029B Datasheet - Page 5

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SL4029B

Manufacturer Part Number
SL4029B
Description
Presettable Up/Down Counter
Manufacturer
System Logic Semiconductor
Datasheet
SL4029B
TIMING REQUIREMENTS
*
**
From Up/Down, Binary/Decode, Carry In, or Preset Enable Control Inputs to Clock Edge.
From Carry In to Clock Edge
Symbol
t
t
r
t
t
rem
, t
t
t
t
su
h
su
w
w
**
*
f
**
*
Minimum Pulse Width, Clock (Figure 1)
Minimum Pulse Width, Preset Enable
(Figure 1)
Minimum Setup Time, Clock to B/D or U/D
(Figure 1)
Minimum Removal Time, Preset Enable (Figure 1)
Minimum Hold Time, Clock to Carry In (Figure 2)
Minimum Setup Time, Carry In to Clock (Figure
1)
Maximum Input Rise and Fall Times,Clock
(Figure 2)
Parameter
(C
L
=50pF, R
L
=200 k , Input t
V
r
5.0
5.0
5.0
5.0
5.0
5.0
5.0
10
15
10
15
10
15
10
15
10
15
10
15
10
15
=t
V
CC
f
=20 ns)
-55 C
180
130
340
140
100
200
110
200
90
60
70
50
80
50
30
25
70
60
15
15
15
Guaranteed Limit
25 C
180
130
340
140
100
200
110
200
90
60
70
50
80
50
30
25
70
60
15
15
15
SLS
System Logic
Semiconductor
125 C
360
180
120
260
140
100
680
280
200
400
220
160
100
400
140
120
60
50
30
30
30
Unit
ns
ns
ns
ns
ns
ns
s

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