ST7571 Sitronix Technology, ST7571 Datasheet - Page 48

• Manufacturer Part Number: ST7571
• Description: 4 Gray Scale Dot Matrix LCD Controller/Driver
• Manufacturer: Sitronix Technology

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ST7571
10. OPERATION FLOW
10.1 Power ON Sequence
Timing Requirement:
Note:
1.
2.
3.
4.
Ver 1.5a
Case 1: RST=L while Power ON (Recommended)
RST input time
VDD2 power delay
IC will NOT be damaged if either VDDI or VDDA is OFF while another is ON.
The specification listed below just wants to prevent abnormal display on LCD module.
Power stable is defined as the time that the later power (VDDI or VDDA) reaches 90% of its rated voltage. The power
stable time depends on system and the time is not included in this specification (customer should consider this factor).
It is recommended to keep the interface pins (A0, RWR, ERD, CSB and DB[7:0]), except RST, at “High” level before
the internal reset procedure is finished.
Internal VD1 generator will generate VD1 when DCPS is set to “L”. The VD1 rising time is controlled by ITO resistance
and the external capacitor. Before VD1 is stable, internal logic state is unstable and large current maybe occurred. This
current will not damage IC. This period can be reduced by reduce the ITO resistance or the external capacitor value.
Item
Symbol
t
ON-RST
t
ON-V2
0 ≤ t
Requirement
Recommend
ON-RST
0 ≤ t
ON-V2
≤ 50 ms
l
l
l
l
l
l
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Case 2: RST=H while Power ON
After VDDI is stable, a successful hardware reset by RST is
required.
RST=L can be input at any time after power is stable.
t
The recommended time just prevents abnormal display
(customer can use Case 1 instead).
Applying VDDI and VDDA in any order will not damage IC.
If VDDI and VDDA are separated, it is recommend to turn
ON VDDI first, followed by a success hardware reset, and
the VDDA is the last one.
RW
& t
R
should match the timing specification of RST.
Note
2009/7/21