T35L6432A-5T Taiwan Memory Technology, Inc., T35L6432A-5T Datasheet - Page 12

• Manufacturer Part Number: T35L6432A-5T
• Description: 64K x 32 SRAM
• Manufacturer: Taiwan Memory Technology, Inc.

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WRITE TIMING
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
B W 1- B W 4
A D D RE S S
( N O T E 2 )
2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW , CE2 is LOW
3. OE must be HIGH before the input data setup and hold HIGH throughout the data hold time. This
4.
5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE , BW1- BW4 LOW.
B W E ,
A D S P
A DS C
address following A2.
and CE2 is HIGH. When CE is HIGH , CE2 is HIGH and CE2 is LOW.
prevents input/output data contention for the time period to the byte write enable inputs being
sampled.
A DV
ADV
C L K
G W
O E
C E
Q
D
CH
TE
must be HIGH to permit a WRITE to the loaded address.
BUR ST RE A D
Hi g h-Z
t A DS S t A DS H
t CE S t CE H
t A S t A H
A 1
t KH
(NOT E 3)
t O E HZ
BY T E W RIT E si g n als a r e
ig n or ed f or f ir st cy cle w hen
A DS P i n it i alte s bu r st.
t KC
t A D SS t A D S H
t D S
t KL
S in g le W RIT E
D(A1)
t DH
A 2
(NO TE 4)
D(A2)
t W S t W H
(NOT E 1)
D(A2+1)
BU RS T W RIT E
P. 12
(N OT E 5)
D(A2+1)
AD V su sp nd s b u rst .
D(A2 +2)
A DS C exte n ds b ur s t.
D(A2+3 )
t A D SS t A D SH
Publication Date: DEC. 1998
A 3
D(A3 )
E xte nd e d BU RST W RIT E
t A A S t A A H
t W S t W H
T35L6432A
D(A3+1)
DON' T CARE
UNDEFINED
Revision:A
D (A3+2 )