HCF40103BEY STMicroelectronics, HCF40103BEY Datasheet
HCF40103BEY
Specifications of HCF40103BEY
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HCF40103BEY Summary of contents
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... When the CLEAR (CLR) input is low, the counter is asynchronously cleared to its maximum count (255 input. The precedent relationship between control input is indicated in the truth table. If all control HCF40103B DIP SOP TUBE T & R HCF40103BEY HCF40103BM1 HCF40103M013TR ) regardless of the state of any other 10 1/14 ...
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HCF40103B inputs are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 256 clock pulses long. IINPUT EQUIVALENT CIRCUIT FUNCTIONAL DIAGRAM TRUTH TABLES CONTROL INPUTS CLR APE SPE H ...
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LOGIC DIAGRAM LOGIC DIAGRAM FOR FLIP-FLOPS, FF0-FF7 HCF40103B 3/14 ...
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HCF40103B TIMING CHART ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Input Current I P Power Dissipation per Package D Power Dissipation per Output Transistor T Operating Temperature op T Storage Temperature stg ...
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DC SPECIFICATIONS Symbol Parameter V (V) I Quiescent Current 0/5 L 0/10 0/15 0/20 V High Level Output 0/5 OH Voltage 0/10 0/15 V Low Level Output 5/0 OL Voltage 10/0 15/0 V High Level Input IH Voltage V Low ...
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HCF40103B DYNAMIC ELECTRICAL CHARACTERISTICS (T Symbol Parameter t t Propagation Delay Time PHL PLH Clock To Out t t Propagation Delay Time PHL PLH Carry In/counter Enable To Output t t Propagation Delay Time PHL PLH Asynchronous Preset Enable To ...
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TYPICAL APPLICATIONS DIVIDE BY "N" COUNTER MICROPROCESSOR INTERRUPT TIMER MICROPROCESSOR INTERRUPT TIMER SYNCHRONOUS CASCADING SYNCHRONOUS CASCADING * An Output spike (160ns 5V) occurs whenever two or DD more devices are cascaded in the parallel clocked mode because ...
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HCF40103B TEST CIRCUIT C = 50pF or equivalent (includes jig and probe capacitance 200K pulse generator (typically OUT WAVEFORM 1 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 8/14 ...
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WAVEFORM 2 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle) WAVEFORM 3 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle) HCF40103B 9/14 ...
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HCF40103B WAVEFORM 4 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) WAVEFORM 5 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle) 10/14 ...
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WAVEFORM 6 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle) HCF40103B 11/14 ...
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HCF40103B DIM. MIN. a1 0. 12/14 Plastic DIP-16 (0.25) MECHANICAL DATA mm. TYP MAX. 1.65 0.5 0.25 20 8.5 2.54 17.78 7.1 5.1 3.3 1.27 inch MIN. TYP. ...
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SO-16 MECHANICAL DATA DIM. MIN 0 0. 9 3.8 G 4 mm. TYP MAX. MIN. 1.75 0.2 0.003 1.65 0.46 0.013 0.25 ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...