ST24C02 ST Microelectronics, ST24C02 Datasheet - Page 6

• Manufacturer Part Number: ST24C02
• Description: SERIAL 2K (256 x 8) EEPROM
• Manufacturer: ST Microelectronics

ST24/25C02, ST24C02R, ST24/25W02
Table 7. AC Characteristics
(T
Notes: 1. For a reSTART condition, or following a write cycle.
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages 0.3V
Figure 4. AC Testing Input Output Waveforms
6/16
A
0.8V CC
0.2V CC
Symbol
t
t
= 0 to 70 C, –20 to 85 C or –40 to 85 C; V
t
t
t
t
CHDX
CLQV
CH1CH2
DH1DH2
CL1CL2
DL1DL1
t
t
t
t
t
t
t
t
t
CHDH
CHCL
CLDX
CLCH
DXCX
DHDL
CLQX
DLCL
W
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
f
C
(3)
conditions.
maximum programming time is doubled to 20ms.
(2)
(1)
t
t
t
t
t
SU:STA
HD:STA
HD:DAT
SU:DAT
SU:STO
t
t
t
f
HIGH
t
Alt
LOW
t
t
BUF
SCL
WR
t
t
t
t
AA
DH
R
R
F
F
Clock Rise Time
Clock Fall Time
Input Rise Time
Input Fall Time
Clock High to Input Transition
Clock Pulse Width High
Input Low to Clock Low (START)
Clock Low to Input Transition
Clock Pulse Width Low
Input Transition to Clock Transition
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Next Data Out Valid
Data Out Hold Time
Clock Frequency
Write Time
0.2V
50ns
CC
CC
to 0.8V
to 0.7V
0.7V CC
0.3V CC
AI00825
Parameter
CC
CC
CC
= 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
DEVICE OPERATION (cont’d)
The 4 most significant bits of the device select code
are the device type identifier, corresponding to the
I
are fixed as 1010b. The following 3 bits identify the
specific memory on the bus. They are matched to
the chip enable signals E2, E1, E0. Thus up to 8 x
2K memories can be connected on the same bus
giving a memory capacity total of 16K bits. After a
START condition any memory on the bus will iden-
tify the device code and compare the following 3
bits to its chip enable inputs E2, E1, E0.
The 8th bit sent is the read or write bit (RW), this
bit is set to ’1’ for read and ’0’ for write operations.
If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time.
2
C bus definition. For these memories the 4 bits
Min
250
300
4.7
4.7
4.7
4.7
0.3
4
4
0
Max
300
300
100
3.5
10
1
1
Unit
kHz
ms
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s