C1068 Linear Technology, C1068 Datasheet - Page 6

• Manufacturer Part Number: C1068
• Description: Search -----> LTC1068
• Manufacturer: Linear Technology

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LTC1068 Series
ELECTRICAL CHARACTERISTICS
PARAMETER
DC Offset Voltage (Note 5)
(See Table 1)
Clock Feedthrough
Max Clock Frequency (Note 6)
Power Supply Current
The
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Production testing for single 3.14V supply is achieved by
using the equivalent dual supplies of 1.57V.
Note 3: Production testing for single 4.75V supply is achieved by
using the equivalent dual supplies of 2.375V.
Table 1. Output DC Offsets One 2nd Order Section
6
TYPICAL PERFORMANCE CHARACTERISTICS
50
45
40
35
30
25
20
15
10
MODE
5
0
1b
1
2
3
denotes specifications which apply over the full operating
0
LTC1068
Maximum Q vs Center Frequency
(Modes 1, 1b, 2)
10
CENTER FREQUENCY, f
V
V
V
[V
[R4/(R2 + R4)] + V
V
A
A. V
B. V
C. V
(FOR MODE 2 R4
20
OSN
OS1
OS1
OS2
OS1
S
S
S
[(1/Q) + 1 + ||HOLP||] – V
[(1/Q) + 1 + R2/R1] – V
(1 + R2/R1 + R2/R3 + R2/R4) – V
= 3.3V, f
= 5V, f
= 5V, f
30
CLK(MAX)
B
40
CLK(MAX)
CLK(MAX)
O
10R2)
50
(kHz)
OS2
= 3.4MHz
W
= 5.6MHz
= 1.5MHz
[R2/(R2 + R4)]
C
60
1068 G01
U
OS3
70
OS3
/Q
CONDITIONS
V
(DC Offset of Input Inverter)
V
(DC Offset of First Integrator)
V
(DC Offset of Second Integrator)
V
V
V
V
V
/Q
S
S
S
S
S
S
S
S
= 5V, f
= 5V, f
= 5V, f
= 5V, f
= 5V, Q 1.6, Mode 1
= 3.14V, f
= 4.75V, f
= 5V, f
OS3
50
45
40
35
30
25
20
15
10
(R2/R3)X
5
0
LTC1068
Maximum Q vs Center Frequency
(Modes 2, 3)
0
CLK
CLK
CLK
CLK
CLK
CLK
CLK
= 1MHz, V
= 1MHz, V
= 1MHz, V
= 1MHz
= 1MHz
LTC1068-25 (Complete Filter) V
= 1MHz (Note 2)
= 1MHz (Note 3)
10
CENTER FREQUENCY, f
A
A. V
B. V
C. V
(FOR MODE 2 R4 < 10R2)
20
OS1
OS2
OS3
V
S
S
S
V
V
V
V
OSBP
= 3.3V, f
= 5V, f
= 5V, f
OS3
OS3
OS3
OS3
30
Note 4: Pin 7 (AGND) is the internal analog ground of the device. For
single supply applications this pin should be bypassed with a 1 F
capacitor. The biasing voltage of AGND is set with an internal resistive
divider from Pin 8 to Pin 23 (see Block Diagram).
Note 5: Side D is guaranteed by design.
Note 6: See Typical Performance Characteristics.
B
CLK(MAX)
CLK(MAX)
CLK(MAX)
40
O
V
V
~(V
V
V
OSLP
OSN
OSN
OS1
(kHz)
= 3MHz
OSN
= 5MHz
= 1MHz
[1 + R4/R1 + R4/R2 + R4/R3] – V
50
– V
– V
C
– V
1068 G02
OS2
OS2
OS2
60
)(1 + R5/R6)
S
= 5V, T
MIN
55
50
45
40
35
30
25
20
15
10
5
0
0
LTC1068-200
Maximum Q vs Center Frequency
(Modes 1, 1b, 2)
A
= 25 V
4
A
CENTER FREQUENCY, f
TYP
0.25
5.6
3.5
6.5
9.5
– 2
– 5
8
,
0
A: V
B: V
C: V
OS2
unless otherwise noted.
12
S
S
S
(R4/R2) – V
B
= 3.3V, f
= 5V, f
= 5V, f
(FOR MODE 2, R4
16
C
CLK(MAX)
MAX
CLK(MAX)
CLK(MAX)
11
15
15
25
40
8
20
O
OS3
(kHz)
24
= 3.2MHz
(R4/R3)
= 6.1MHz
= 1.2MHz
10R2)
mV
UNITS
28
1068 G03
MHz
RMS
mV
mV
mV
mA
mA
mA
32