STA027 ST Microelectronics, STA027 Datasheet - Page 19

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STA027

Manufacturer Part Number
STA027
Description
SBC Codec
Manufacturer
ST Microelectronics
Datasheet

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STA027
5.3.2
5.3.3
Type : RW - DEC
Software Reset : 0
Description :
This register must contain a PEL value that enables the system PLL to generate a frequency of
50 MHz for the SYSCK. See table 4.
Default value at soft reset assume :
PLL_SYSTEM_PEH_50 :
Address : 0xE7 (231)
Type : RW - DEC
Software Reset : 0
Description :
This register must contain a PEH value that enables the system PLL to generate a frequency of
50 MHz for the SYSCK. See table 4.
Default value at soft reset assume :
PLL_SYSTEM_NDIV_50 :
Address : 0xE8 (232)
Type : RW - DEC
Software Reset : 0
Description :
This register must contain a NDIV value that enables the system PLL to generate a frequency
of 50 MHz for the SYSCK. See table 4.
Default value at soft reset assume :
b7
b7
external crystal provide a CRYCK running at 14.31818 MHz
external crystal provide a CRYCK running at 14.31818 MHz
external crystal provide a CRYCK running at 14.31818 MHz
b6
b6
b5
b5
CD00066274
b4
b4
b3
b3
b2
b2
5 Register description
b1
b1
b0
b0
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