SC2616 Semtech, SC2616 Datasheet - Page 11

• Manufacturer Part Number: SC2616
• Description: Complete DDR Power Solution
• Manufacturer: Semtech

Description
The Semtech SC2616 DDR power supply controller is
the latest and most complete switching and linear
regulator combination, providing the necessary functions
to comply with S3 and S5 sleep state signals generated
by the Desktop Computer Motherboards. VDDQ supply,
and VTT termination voltage are supplied to the Memory
bus during S0 (normal operation) state. During S0, VDDQ
is supplied via the Switching regulator, sourcing high
output currents to the VDD bus as well as supplying the
termination supply current. The SC2616 is capable of
driving a 4000pf capacitor in 25ns (typical, top gate).
This drive capability allows 15-20A DC load on the VDDQ
supply. The VTT termination voltage is an internal sink/
source linear regulator, which during S0 state receives
its power from the VDDQ bus. It is capable of sourcing
and sinking 2 Amps (max). The current limit on this pin is
set to 3 Amps (typical).
Output Current and PCB layout
The current handling capacity of SC2616 depends upon
the amount of heat the PC board can sink from the
SC2616 thermal pad. (See mounting instructions). The
PC board layout must take into consideration the high
current paths, and ground returns for both the VDDQ
and VTT supply pins. VTT, LGND, VDDQ, 5VCC and PGND
traces must also be routed using wide traces to minimize
power loss and heat in these traces, based on the current
handling requirements.
S3 and S5 States
During S3 and S5 sleep states, the operation of the VDDQ
and VTT supplies is governed by the internal sequencing
logic in strict adherence with motherboard specifications.
The timing diagram demonstrates the state of the
controller, and each of the VDDQ and VTT supplies during
S3 and S5 transitions. When S3 is low, the VDDQ supplies
the “Suspend To RAM” current of 650 mA (min) to
maintain the information in memory while in standby
mode. The VTT termination voltage is not needed during
this state, and is thus tri-stated during S3. Once S3 goes
high, the VDDQ switcher recovers and takes control of
the VDDQ supply voltage. When S5 and S3 are pulled
low, all supplies shut down. The SS/EN pin must be pulled
low (<0.3V) and high again to restart the SC2616. This
can be achieved by cycling the input supplies, 5V and
POWER MANAGEMENT
Applications Information
2003 Semtech Corp.
11
12V since both supplies have to be higher than their UVLO
thresholds for proper start-up.
Initial Conditions and Event Sequencing
The main switcher will start-up in Asynchronous Mode
when the voltage on SS/EN pin is greater than ~0.3V.
The SS/EN will go high only after the 5Vcc and 12Vcc are
higher than their respective UVLO thresholds. The switcher
achieves maximum duty cycle when SS/EN reaches 0.8V.
When the SS/EN equals 1.25V, the synchronous FET will
also be activated.
When the S5 and S3 go high for the first time, the VDDQ
is supplied by the switcher, thus removing the burden of
charging the output capacitors via the linear regulator.
An internal latch guarantees that the supply goes through
S0 state for the first time.
During a transition from S3 to S0, where the 5V and 12V
rails and subsequently the SS/EN pin go high, the internal
VDDQ standby supply will remain ”on” until SS/EN has
reached 1V, at which point only the switcher is supplying
VDDQ , andthe internal “power good” indicator goes high.
The “Memory” activity should be slaved off the “Power
OK” signal from the Silver Box supply, and since the “Power
OK” is asserted after all supplies are within close tolerance
of their final values, the VDDQ switcher should have
been running for some time before the memory is
activated. This is true for typical SS/EN capacitor values
(10nf to 220nf). Thus during transitions from S3 to S0,
the concern that the VDDQ Standby supply may have to
provide high currents before the switcher is activated is
alleviated.
The logic inputs to S3 and S5 pins must be defined before
application of power to the SC2616. This can be
guaranteed by pulling up the S3 and S5 inputs to
5VStandby. If the chipset that asserts these signals is
powered after the SC2616 powers up, and S3 and S5
are not pulled up, erroneous startup and operation can
result.
Care must be taken not to exceed the maximum voltage/
current specifications on to the interface supplying these
signals. The pullup voltage and resistor must be chosen
such that when high, the S3 and S5 do not “back drive”
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SC2616