P601-01SC PhaseLink Corp., P601-01SC Datasheet - Page 2

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P601-01SC

Manufacturer Part Number
P601-01SC
Description
Low Phase Noise Pll Clock Multiplier - Phaselink Corporation
Manufacturer
PhaseLink Corp.
Datasheet
PIN DESCRIPTIONS
MULTIPLIER SELECT TABLE
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 2
REFOUT
REFEN
S3
Name
XOUT
GND
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
VDD
CLK
XIN
OE
S1
S2
S3
S0
S2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
Number
14,15,16
3,4,5
10
11
12
13
1
2
6
7
8
9
S1
Type
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
O
O
P
O
P
I
I
I
I
I
I
I
Clock output. Equals the input frequency times selected multiplier.
Reference clock enable. When Low, it disables REFOUT. When High, it
enables REFOUT.
Power Supply.
Crystal output.
Multiplier Select Pin 1. Determines CLK output. Has internal pull-up.
Crystal input to be connected to 10-27MHz fundamental parallel mode crys-
tal (C
Multiplier Select Pin 2. Determines CLK output. Has internal pull-up.
Multiplier Select Pin 3. Determines CLK output. Has internal pull-up.
Multiplier Select Pin 0. Determines CLK output. Has internal pull-up.
Output Enable. Tri-state CLK and REFOUT when low. Has internal pull-up.
Buffered crystal oscillator clock output. Controlled by REFEN.
Ground.
L
=15pF). On chip load capacitors: No external capacitor required.
S0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
Low Phase Noise PLL Clock Multiplier
Description
Input x 11
Input x 10
Input x 12
Input x 16
Input x 1
Input x 3
Input x 4
Input x 5
Input x 6
Input x 8
Input x 7
Input x 2
Input x 9
Input x 8
CLK
Test
PLL601-01

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