TMSH Xilinx Inc, TMSH Datasheet
TMSH
Related parts for TMSH
TMSH Summary of contents
Page 1
September 17, 1999 (Version 1.3) Features • In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range • IEEE Std 1149.1 boundary-scan (JTAG) support • ...
Page 2
XC1800 Series of In-System Programmable Configuration PROMs Pinout and Pin Description Table 1: Pin Names and Descriptions Boundary Pin Scan Function Name Order D0 4 DATA OUT D0 is the DATA output pin to provide data 3 OUTPUT ENABLE D1 ...
Page 3
R XC1800 Series of In-System Programmable Configuration PROMs Boundary Pin Scan Function Name Order CEO 13 DATA OUT Chip Enable (CEO) output is connected to the CE input of the next PROM in the 14 OUTPUT chain. This output is ...
Page 4
XC1800 Series of In-System Programmable Configuration PROMs Xilinx FPGAs and Compatible PROMs Device Configuration Bits XC4003E 53,984 XC4005E 95,008 XC4006E 119,840 XC4008E 147,552 XC4010E 178,144 XC4013E 247,968 XC4020E 329,312 XC4025E 422,176 XC4002XL 61,100 XC4005XL 151,960 XC4010XL 283,424 XC4013XL/XLA 393,632 XC4020XL/XLA ...
Page 5
... External Programming Xilinx reprogrammable PROMs can also be programmed by the Xilinx HW-130 device programmer. This provides the added flexibility of using pre-programmed devices in design, boundary-scan manufacturing tools, with an in-sys- tem programmable option for future enhancements and design changes. (a) Figure 2: In-System Programming Operation (a) solder device to PCB and (b) Program using Download Cable September 17, 1999 (Version 1 ...
Page 6
XC1800 Series of In-System Programmable Configuration PROMs IEEE 1149.1 Boundary-Scan (JTAG) The XC1800 family is fully compliant with the IEEE Std. 1149.1 Boundary-Scan, also known as JTAG. A Test Access Port (TAP) and registers are provided to support all required ...
Page 7
... The AC characteristics of the XC1800 TAP are described as follows. TAP Timing Figure 4 shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both boundary-scan and ISP operations. TMSH TMSS TDIS TDIH TDOV TDOZX Min Max ...
Page 8
XC1800 Series of In-System Programmable Configuration PROMs Controlling Configuration PROMs Connecting the FPGA device with the configuration PROM. • The DATA output(s) of the of the PROM(s) drives the DIN input of the lead FPGA device. • The Master FPGA ...
Page 9
R XC1800 Series of In-System Programmable Configuration PROMs interconnected. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and disables its DATA line. The second PROM recognizes ...
Page 10
XC1800 Series of In-System Programmable Configuration PROMs Vcc D OUT FPGA MODES DIN CCLK DONE INIT PROGRAM (Low Resets the Address Pointer) Master Serial Mode 3. WRITE M1 4.7k 4.7k M2 VIRTEX Select MAP NC BUSY DONE CCLK ...
Page 11
R XC1800 Series of In-System Programmable Configuration PROMs 5V Tolerant I/Os The I/Os on each re-programmable PROM are fully 5V tol- erant even through the core power supply is 3.3 volts. This allows 5V CMOS signals to connect directly to ...
Page 12
XC1800 Series of In-System Programmable Configuration PROMs Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum ...
Page 13
R XC1800 Series of In-System Programmable Configuration PROMs DC Characteristics Over Operating Conditions Symbol Parameter V High-level output voltage for 3.3 V outputs OH High-level output voltage for 2.5 V outputs V Low-level output voltage for 3.3V outputs OL Low-level ...
Page 14
XC1800 Series of In-System Programmable Configuration PROMs AC Characteristics Over Operating Conditions . CE 9 RESET/OE CLK DATA Symbol Data Delay Data Delay ...
Page 15
R XC1800 Series of In-System Programmable Configuration PROMs AC Characteristics Over Operating Condition When Cascading RESET/OE CE CLK 12 T DATA 13 T CEO Symbol 12 T CLK to Data Float Delay CDF 13 T CLK to CEO Delay OCK ...
Page 16
XC1800 Series of In-System Programmable Configuration PROMs Ordering Information Device Number XC1804 XC1802 XC1801 XC18512 XC18256 XC18128 Valid Ordering Combinations XC1804VQ44C XC1802VQ44C XC1804PC44C XC1802PC44C XC1804VQ44I XC1802VQ44I XC1804PC44I XC1802PC44I Marking Information 44-Pin Package Device Number XC1804 XC1802 20-Pin Package Device Number ...