R2051 RICOH Co.,Ltd., R2051 Datasheet
R2051
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R2051 Summary of contents
Page 1
... Real-Time Clock ICs with Battery Backup switch-over Function OUTLINE The R2051 is a CMOS real-time clock IC connected to the CPU by two signal lines, SCL and SDA, and configured to perform serial transmission of time and calendar data to the CPU. Further, battery backup switchover circuit and a voltage detector are incorporated ...
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... TOP VIEW BLOCK DIAGRAM C2 SW2 VSB BATTERY R1 VOLTAGE MONITOR OSCIN REAL TIME CLOCK OSCOUT VOLTAGE CIN C1 REFERENCE VSS ( ) are for the R2051Txx only 2 R2051Kxx(FFP12) CLKOUT CIN VDD 10 6 VSS VCC 11 5 VDCC VSB 12 4 TOP VIEW VDD SW1 VOLTAGE DETECTOR ...
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... SELECTION GUIDE In the R2051xxx Series, output voltage and options can be designated. Part Number is designated as follows: R2051K01-E2 mPart Number R2051abb-cc Code Designation of the package. K: FFP12 a S: SSOP16 T: TSSOP10G bb Serial number of Voltage detector setting etc. cc Designation of the taping type. Only E2 is available. ...
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... The OSCIN and OSCOUT pins are used Circuit to connect the 32.768-kHz quartz crystal Input / Output unit (with all other oscillation circuit OSCOUT components built into the R2051). VDD Positive Power The VDD pin is connected to the power Supply Input supply. Connect a capacitor as much as ...
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... Vaccess specification is guaranteed by design. DET1 *2) CGout is connected between OSCIN and VSS, CDout is connected between OSCOUT and VSS. R2051 series incorporates the capacitors between OSCIN and VSS, between OSCOUT and VSS. Then normally, CGout and CDout are not necessary. *3) Quartz crystal unit: CL=6-8pF, R1=30K: ...
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... V VDD Output DDOUT1 Voltage 1 V VDD Output DDOUT2 Voltage 2 CG Internal Oscillation Capacitance 1 CD Internal Oscillation Capacitance 2 *1) Guaranteed by design. *2) Except R2051T01 6 =V =3.0V, 0.1uF between VDD and VSS, CIN and VSS Pin Name Conditions SCL,SDA CLKOUT V =V -0. CLKOUT V =0 ...
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... Output=OPEN DD VDD Topt=+25qC VDD Topt=+25qC VCC Topt=+25qC VCC Topt=+25qC VCC, Topt=-40 to +85qC VSB *1) VDD Topt=+25qC Iout=1.0mA VDD Topt=+25qC =3.3V, Iout=0.1mA SB OSCIN OSCOUT R2051 Series Min. Typ. Max. 0.8x 5 -0.3 0. -0.5 0.5 2.0 3.0 0.5 -1.0 1.0 -1.0 1.0 -1.0 1.0 0.4 1.0 -1.00 1.00 1.90 2.10 2 ...
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... R2051 Series x R2051S03 (Unless otherwise specified: V =0V Topt=-40 to +85qC) Symbol Item V “H” Input Voltage IH V “L” Input Voltage IL I “H” Output OH Current I “L” Output OL1 Current I OL2 I OL4 I OL3 I Input Leakage IL Current I Output Off-state OZ1 ...
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... RCV Stop Condition to Start Condition t Output Delay Time of DELAY *2) Voltage Detector *1) VCC voltage interfacing with CPU is defined by Vaccess (P.5 RECOMMENDED OPERATING CONDITIONS) *2) Except R2051Txx *) For reading/writing timing, see “P.34 Interfacing with the CPU xData Transmission under Special Condition”. ,V =0.2uV ,V =0.8uV ,V =0.2uV CC ...
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... R2051 Series S SCL t LOW SDA(IN HD;STA SU;DAT SDA(OUT) t PL;DAT Start Condition S Repeated Start Condition Sr +V DET1 VCC VDCC HIGH HD;STA t t HD;DAT SU;STA t PZ;DAT Stop Condition P t DELAY SU;STO ...
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... PACKAGE DIMENSIONS x R2051Kxx 9 10 1PIN INDEX 12 1 0.2r0.15 (BOTTOM VIEW) 0.17r0.1 0.27r0.15 2.0r0 2PIN INDEX 0.35 R2051 Series 0.05 0.35 0.25 1.0Max unit ...
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... R2051 Series x R2051Sxx 5.0r0 0.65 0.225typ 0.10 +0.1 0.22 -0.05 0. 10q +0.1 0.15 -0.05 unit: mm ...
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... R2051Txx 2.9r0 0.5 0.1 0.2r0.1 0. 10q +0.1 0.13 -0.05 unit: mm R2051 Series 13 ...
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... Clock and Calendar Function The R2051 reads and writes time data from and to the CPU in units ranging from seconds to the last two digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two digits are a multiple of 4 ...
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... Power-on Reset, Oscillation Halt Sensing Function and Supply Voltage Monitoring Function The R2051 has 3 power supply pins (VCC, VSB, VDD), among them, VCC pin and VDD pin have monitoring function of supply voltage. VCC power supply monitoring circuit makes VDCC pin “L” when VCC power supply pin becomes equal or lower than – ...
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... R2051 Series form adapted to interruption from the CPU in the level mode (with second, minute, hour, and month interrupts). The condition of periodic interrupt signals can be monitored with using a polling function. R2051Txx has the periodic interrupt registers, but does not have INTR output pin. ...
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... WH20 WH10 WP WW6 WW5 WW4 - DM40 DM20 DM10 - - DH20 DH10 DP WALE DALE SCRA 12 /24 TCH2 VDSL VDET PON XST *5) R2051 Series MO8 MO4 MO2 MO1 Y8 Y4 ...
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... R2051 Series Register Settings x Control Register 1 (Address Eh WALE DALE 12 /24 WALE DALE 12 / Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts. (1) WALE, DALE Alarm_W Enable Bit, Alarm_D Enable Bit ...
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... Once per hour (at 00 minutes and 00 *2) seconds of every hour) Level Mode Once per month (at 00 hours, 00 *2) minutes, and 00 seconds of first day of every month) Rewriting of the second counter Setting CTFG bit to 0 (Increment of (Increment of second counter) second counter) R2051 Series (Default) 19 ...
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... Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of r3.784 ms. For example, 1-Hz clock pulses will have a duty cycle of 50 r0.3784%. Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of r3.784 ms. R2051Txx does not have INTR output pin x Control Register 2 (Address Fh) ...
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... INTR pin until it is enabled (“L”) again in the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event. R2051Txx has CTFG bit, but does not have INTR output pin ...
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... R2051 Series x Time Counter (Address 0-2h) Second Counter (Address 0h S40 S20 0 S40 S20 0 Indefi Indefi nite nite Minute Counter (Address 1h M40 M20 0 M40 M20 0 Indefi Indefi nite nite Hour Counter (Address 2h H20 H20 ...
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... Y10 Y10 Indefi Indefi Indefi Indefi nite nite nite nite R2051 Series D0 D1 (For Writing) D1 (For Reading) Indefi Default Settings *) nite D0 MO1 (For Writing) MO1 (For Reading) Indefi Default Settings *) nite D0 Y1 (For Writing) Y1 (For Reading) ...
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... R2051 Series x Oscillation Adjustment Register (Address 7h DEV F6 F5 DEV Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts. DEV bit When DEV is set to 0, the Oscillation Adjustment Circuit operates 00, 20, 40 seconds. ...
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... D3 D2 WW4 WW3 WW2 WW1 WW4 WW3 WW2 WW1 Indefi Indefi Indefi Indefi nite nite nite nite R2051 Series D1 D0 WM1 (For Writing) WM1 (For Reading) Indefi Default Settings *) nite D1 D0 WH1 (For Writing) WH1 (For Reading) Indefi Default Settings *) nite ...
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... R2051 Series Example of Alarm Time Setting Alarm Preset alarm Sun. Mon. Tue. Wed. time 00:00 a.m. on all 1 1 days 01:30 a.m. on all 1 1 days 11:59 a.m. on all 1 1 days 00:00 p.m. on Mon Fri. 01:30 p.m. on Sun 11:59 p. Mon. ,Wed., and Fri. Note that the correspondence between WW0 to WW6 and the days of the week shown in the above table is only an example and not mandatory ...
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... Interfacing with the CPU 2 The R2051 employs the I C-Bus system to be connected to the CPU via 2-wires. Connection and system C-Bus are described in the following sections Connection of I C-Bus 2-wires, SCL and SDA pins that are connected to I respectively. All ICs that are connected to these lines are designed that will not be clamped when a voltage beyond supply voltage is applied to input or output pins ...
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... R2051 Series duration of SDA and SCL pins are the half of bus operation duration. “u 2” in the numerator of the same member is because there are two pins of SDA and SCL. The third member, (charging/discharging times per unit time) means number of transition from “H” to “L” of the signal line. ...
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... The slave side (transmission side) continues to release the SDA pin so that the master will be able to generate Stop Condition, after falling edge of the SCL 9bit of clock pulses. tHD;DAT Stop Condition tSU;STO Any bytes of data may be serially R2051 Series 29 ...
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... MSB and 2 and after bytes are read, when 8bit is “H” and when write “L”. The Slave Address of the R2051 is specified at (0110010). At the end of data transmission / receiving, Stop Condition is generated to complete transmission. However, if start condition is generated without generating Stop Condition, Repeated Start Condition is met and transmission / receiving data may be continue by setting the Slave Address again ...
Page 31
... C-Bus standard defines a transmission format for the slave allocated for each IC, transmission method of address information not defined. The R2051 transmits data the internal address pointer (4bit) and the Transmission Format Register (4bit) at the 1byte next to one which transmitted a Slave Address and a write command ...
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... R2051 Series (5) Data transmission read format of the R2051 The R2051 allows the following three read out method of data an internal register. The first method to reading data from the internal register is to specify an internal address by setting the internal address pointer and the transmission format register described P31 (4), generate the Repeated Start Condition (See P30 (3)) to change the data transmission direction to perform reading ...
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... Internal Address Fh. Data Transmission Reading of data from Format the internal address Eh Registerm4h Data A A Reading of data from Reading of data from the internal address 0h the internal address 1h Slave to Master P Stop Condition R2051 Series 2 A Data /A P C-Bus 33 ...
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... Assuming read was started at 05:59:59 P.M. and while reading seconds and minutes the time advanced to 06:00:00 P.M. At this time second digit is hold so read the read as 05:59:59. Then the R2051 confirms (Stop Condition) and carries second digit being hold and the time change to 06:00:00 P.M. Then, when the hour digit is read, it changes to 6 ...
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... Generally, quartz crystal units have basic characteristics including an equivalent series resistance (R1) indicating the ease of their oscillation and a load capacitance (CL) indicating the degree of their center frequency. Particularly, quartz crystal units intended for use in the R2051 are recommended to have a typical R1 value of 30k: and a typical CL value 8pF. To confirm these recommended values, contact the manufacturers of quartz crystal units intended for use in these particular models. < ...
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... The oscillation frequency of the oscillation circuit can be adjusted by varying procedures depending on the usage of Model R2051 in the system into which they are to be built and on the allowable degree of time count errors. The flow chart below serves as a guide to selecting an optimum oscillation frequency adjustment procedure for the relevant system ...
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... CL = (CG u CD)/( where "CS" represents the floating capacity of the printed circuit board. The quartz crystal unit intended for use in the R2051 is recommended to have the CL value on the order 8pF. Its oscillation frequency should be measured by the method described in " P36 Oscillation Frequency" ...
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... Adjustment Register is set to 0, R2051 varies number of 1-second clock pulses once per 20 seconds. When DEV bit is set to 1, R2051 varies number of 1-second clock pulses once per 60 seconds. The oscillation adjustment circuit can be disabled by writing the settings of "*, *" ("*" representing "0" or "1") to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment circuit ...
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... Oscillation adjustment value can be set from -62 to 63. Then, in this case, Oscillation adjustment value is out of range. (4) Difference between DEV=0 and DEV=1 Difference between DEV=0 and DEV=1 is following, Maximum value range -189.2ppm to +189.2ppm Minimum resolution 3ppm -6 Oscillation frequency u 3.051 Oscillation frequency u 1.017 u 10 DEV=0 -62ppm to +63ppm 1ppm R2051 Series - DEV=1 39 ...
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... If following 3 conditions are completed, actual clock adjustment value could be different from target adjustment value that set by oscillator adjustment function. 1. Using oscillator adjustment function 2. Access to R2051 at random, or synchronized with external clock that has no relation to R2051, or synchronized with periodic interrupt in pulse mode. 3. Access to R2051 more than 2 times per each second on average. ...
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... No drop in VDD supply voltage below threshold voltage and no halt in oscillation Drop in VDD supply voltage below threshold voltage and no halt on oscillation Drop in supply voltage to 0v R2051 Series VDET a drop in supply voltage below a threshold voltage of 2.1 or 1.35v D6 in Address Fh High 0 ...
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... R2051 Series VDD 32768Hz Oscillation Power-on reset flag (PON) Oscillation halt sensing flag (XST) VDD supply voltage monitor flag (VDET) Internal initialization period ( sec.) When the PON bit is set the control register 2, the DEV F0, WALE, DALE, 12 /24, SCRATCH2, TEST, CT2, CT1, CT0, VDSL, VDET, SCRATCH1, CTFG, WAFG, and DAFG bits are reset the oscillation adjustment register, the control register 1, and the control register 2 ...
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... Voltage Monitoring Circuit R2051S/Kxx incorporates two kinds of voltage monitoring function. (R2051Txx incorporates one kind only.) These are shown in the table below. Purpose Monitoring supply voltage Output for result Function Detector Threshold (falling edge of power supply voltage) Detector Released Voltage (rising edge of power ...
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... SW1 SW2 Battery Switch Over Circuit R2051 incorporates three power supply pins, VDD, VCC, and VSB. VDD pin is the power supply pin for internal real time clock circuit. When VCC voltage is lower than rV than rV , VCC supplies the power to VDD. The timing chart for VCC, VDD, and VSB is shown following. ...
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... Alarm and Periodic Interrupt The R2051 incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals for output from the INTR pin as described below. R2051Txx has these functions registers, but does not have the INTR output pin. ...
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... R2051 Series drive high (disable) the alarm interrupt circuit when set to 0. The enable bits will not be affected even when the flag bits are set this event, therefore, the alarm interrupt circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match between current time and preset alarm time ...
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... Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of r3.784ms. For example, 1-Hz clock pulses will have a duty cycle of 50 r0.3784%. Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of r3.784 ms. Rewriting of the second counter Setting CTFG bit to 0 (Increment of (Increment of second counter) second counter) R2051 Series 47 ...
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... CPU (Charging voltage is not equal to power supply voltage) CPU power supply voltage) CPU power VCC supply VSB VDD 0 ML614 etc. VSS R2051 Series VDD SW1 VOLTAGE DETECTOR -V DET1 , and SW1 keeps on. Therefore R1 must be specified by following formula. ) DET1 CPU power 5V supply ...
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... As such, it can be connected to a pull-up resistor 5.5 volts regardless of supply voltage. INTR or VDCC OSCIN 32768Hz OSCOUT VSB VSS Pin (except R2051Txx) System power supply *1) Depending on whether the VDCC pins are to be used during battery backup, it should be connected to a pull-up A resistor at the following different positions: *1) ...
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... R2051 Series Typical Characteristics x Time keeping current (I ) vs. Supply voltage (V SB (Topt=25qC) 0.5 0.4 0.3 0.2 0 VSB(v) x Stand-by current (I ) vs. Supply voltage (V CC (Topt=25qC) 4 R2051x01 3 2 R2051S03 VCC(v) x Time keeping current (I ) vs. Operating Temperature (Topt =3V) SB 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 - Operating Temperature (Celsius) ...
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... Test circuit VCC = INTR VDCC CLKOUT SCL 75 100 SDA 400 500 Test circuit VCC INTR VDCC Frequency CLKOUT counter SCL 75 100 SDA R2051 Series OSCIN OSCOUT VSB VDD 0.1PF CIN 0.1PF VSS OSCIN OSCOUT VSB VDD 0.1PF CIN 0.1PF VSS 51 ...
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... R2051 Series x Frequency deviation ('f/f0) vs. Supply voltage (V (Topt=25qC =3V as standard VCC/VSB(v) x Frequency deviation ('f/f0) vs. CGout (Topt=25qC, V =3V) CGout=0pF as standard -10 -20 -30 - CGout(pF) x Detector threshold voltage (+V (R2051x01) 2.6 2.5 -V DET1 2.4 2.3 -50 - Operating temperature Topt(°C ) ...
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... VCC INTR V =3V VDCC CC CLKOUT SCL 8 10 SDA ) OUT2 Test circuit VCC INTR VDCC CLKOUT SCL 2.5 3 SDA R2051 Series Test circuit VCC OSCIN INTR OSCOUT VDCC VSB CLKOUT VDD 0.1PF SCL CIN 0.1PF SDA VSS OSCIN OSCOUT VSB A VDD 0.1PF CIN ...
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... R2051 Series VDCC pin) (Except R2051Txx (Topt=25qC =2V 0.8 0.6 0.4 0 IOL(mA vs INTR OL OL (Topt=25qC) 0.4 0.3 0.2 0 pin) (Except R2051Txx IOL(mA) ...
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... Take care so that process from Start Condition to Stop Condition will be complete within 0.5sec. Transmission under Special Condition". The R2051 may also be initialized not at power-on but in the process of writing time and calendar data. R2051 Series (Detailed in "P.34 Data ...
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... R2051 Series x Reading Time and Calendar Data (1) Ordinary Process of Reading Time and Calendar Data *1) Start Condition Read from Time Counter and Calendar Counter *2) Stop Condition (2) Basic Process of Reading Time and Calendar Data with Periodic Interrupt Function Set Periodic Interrupt *1) Cycle Selection Bits ...
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... This step is intended to read time data from all the time counters only in the first session of reading time data after writing time data. *4) This step is intended to set the CTFG bit the Control Register Other interrupts 2 to cancel an interrupt to the CPU. Processes *3) R2051 Series 57 ...
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... Set Periodic Interrupt *1) Cycle Selection Bits Generate Interrupt to CPU No CTFG=1? Yes Conduct Periodic Interrupt *2) Control Register 2m (X1X1X011) (2) Alarm Interrupt (except R2051Txx) WALE or DALE m 0 *1) Set Alarm Min., Hr., and Day-of-week Registers WALE or DALE m 1 *2) Generate Interrupt to CPU No WAFG or DAFG=1? Yes Conduct Alarm Interrupt ...