L64777 A LSI Logic Corporation, L64777 A Datasheet - Page 7

• Manufacturer Part Number: L64777 A
• Description: Communications, DVB QAM Modulator
• Manufacturer: LSI Logic Corporation

PLL Mode 2
I/O
Input
Output Signals
In Mode 2, the PCLK input provides an external clock. The L64777 uses
the internal NCO to lock to the transport byte clock, provided at ICLK.
The chip generates an OCLK internally. Select PCLK to be at least twice
the frequency of the internal OCLK.
Consecutive sync blocks can have any gap length between them. Thus,
the L64777 can convert an input block to a block with a gap for RS
insertion, as long as the size of the 128-byte circular input buffer is
sufficient to insert RS gaps and to cope with possible PLL jitter. For an
encoder with 16-parity RS insertion, the L64777 selects the size of the
circular input buffer with sufficient margin.
When operating on public synchronous networks (such as the
synchronous digital hierarchy, SDH, or plesiochronous digital hierarchy,
PDH), the system designer must consider possible jitter on the input
network. The design of the L64777 permits short-term deviations of
input-to-output frequency of
occurs. This is sufficient for operations on SDH or PDH networks.
On ATM networks, you must prebuffer input data to get a continuous
frame rate at the chip input. If high input jitter occurs over an ATM without
a prebuffer, the whole PLL regulation of the input-to-output frame rate
fails. You must design the size of the prebuffer according to the maximum
jitter expected over the asynchronous transfer mode (ATM) network.
The following subsections describe the input and output of the L64777.
The QAM Modulator accepts serial input data at a maximum 54 MHz
clock frequency on the ICLK pin. In Byte-Parallel Input mode (Parallel
mode), the maximum frequency on ICLK is 10 MHz.
The L64777 outputs the I and Q components of its signal on two
separate analog output interfaces. The output interface contains two
internal 10-bit digital-to-analog converters (see
L64777 DVB QAM Modulator
56 bytes before a FIFO overrun condition
Figure
6).
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