MD1213 Supertex, Inc., MD1213 Datasheet

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MD1213

Manufacturer Part Number
MD1213
Description
High Speed Dual MOSFET Driver
Manufacturer
Supertex, Inc.
Datasheet
Features
Applications
Typical Application Circuit
6ns rise and fall time with 1000pF load
2.0A peak output source/sink current
1.2V to 5V input CMOS compatible
4.5V to 13V total supply voltage
Smart logic threshold
Low jitter design
Two matched channels
Outputs can swing below ground
Low inductance package
Thermally-enhanced package
Medical ultrasound imaging
Piezoelectric transducer drivers
Nondestructive evaluation
PIN diode driver
CCD Clock driver/buffer
High speed level translator
3.3V CMOS
Logic Inputs
IN
IN
OE
B
A
Shifter
Shifter
Shifter
Level
Level
Level
V
DD
High Speed Dual MOSFET Driver
Gnd
1
V
SS
MD1213
1
V
V
DD
SS
V
V
2
2
DD
SS
2
2
General Description
The Supertex MD1213 is a high speed, dual MOSFET driver. It is
designed to drive high voltage P and N-channel MOSFET transistors
for medical ultrasound and other applications requiring a high
output current for a capacitive load. The high-speed input stage of
the MD1213 can operate from 1.2V to 5.0V logic interface with an
optimum operating input signal range of 1.8V to 3.3V. An adaptive
threshold circuit is used to set the level translator switch threshold
to the average of the input logic 0 and logic 1 levels. The input logic
levels may be ground referenced, even though the driver is putting out
bipolar signals. The level translator uses a proprietary circuit, which
provides DC coupling together with high-speed operation.
The output stage of the MD1213 has separate power connections
enabling the output signal L and H levels to be chosen independently
from the supply voltages used for the majority of the circuit. As an
example, the input logic levels may be 0 and 1.8volts, the control logic
may be powered by +5.0V and –5.0V, and the output L and H levels
may be varied anywhere over the range of –5.0V to +5.0V. The output
stage is capable of peak currents of up to ±2.0A, depending on the
supply voltages used and load capacitance present.
The OE pin serves a dual purpose. First, its logic H level is used
to compute the threshold voltage level for the channel input level
translators. Secondly, when OE is low, the outputs are disabled, with
the A output high and the B output low. This assists in properly pre-
charging the AC coupling capacitors that may be used in series in the
gate drive circuit of an external PMOS and NMOS transistor pair.
V
V
H
L
V
V
L
H
OUT
OUT
+5V
-5V
A
B
0.47µF
0.47µF
10nF
10nF
Supertex
TC6320
+100V
-100V
1µF
1µF
To Piezoelectric
Transducer
MD1213

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MD1213 Summary of contents

Page 1

... The high-speed input stage of the MD1213 can operate from 1.2V to 5.0V logic interface with an optimum operating input signal range of 1.8V to 3.3V. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels ...

Page 2

... “Green” Packaging 12-Lead QFN (K6 0V 3.3V 25°C) SS1 SS2 OE J Units Conditions 13 V --- 0 V --- V V --- DD - 2.0 V --- - mA 10 µA No input transitions 10 µ One channel on at 5.0Mhz load - mA 5.0 V 0.3 V For logic inputs IN 1.0 µA 1.0 µA MD1213 9 7 and ...

Page 3

... Units Conditions ns Logic input edge speed requirement - 1000pF, LOAD see timing diagram - ns Input signal rise/fall time of 2ns - For each channel - Device to device delay match Output OUT MD1213 OUT ...

Page 4

... Detailed Block Diagram Propagation Delay vs. Logic Voltage 10 9.0 8.0 7.0 6.0 1 1.5 2 2.5 Logic Voltage ( 1.5 1.0 0.6V 0.5 0 1.0 2.0 4.0 3.0 V (volts DD1 DD2 Level Shifter Level Shifter V SS2 V DD2 Level Shifter SUB GND V V SS1 SS2 4 3 3.5 5 OUT OUT MD1213 ...

Page 5

... DD OUT PLH 10 DD1 DD2 MD1213 GND V V SS1 SS2 5 0.47µF +100V 1µF 10nF 10nF -100V 1µF Supertex TC6320 t PHL 90% 10 OUT A OUT MD1213 To Piezoelectric Transducer ...

Page 6

... GND to logic level high, which is 1.2V to 5.0V. Good trace practices should be followed corre- sponding to the desired operating speed. The internal circuit the MD1213 is capable of operating up to 100MHz, with the primary speed limitation being the loading effects of the load capacitance. Because of this speed and the high tran- sient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible ...

Page 7

... MIN 0.80 0.00 Dimension NOM 0.90 0.02 (mm) MAX 1.00 0.05 Drawings not to scale. (The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-MD1213 NR072007 θ Seating A3 Plane L1 Note ...

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