IDT49FCT806 Integrated Device Technology, IDT49FCT806 Datasheet - Page 6
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IDT49FCT806
Manufacturer Part Number
IDT49FCT806
Description
Fast Cmos Buffer/clock Driver
Manufacturer
Integrated Device Technology
Datasheet
1.IDT49FCT806.pdf
(7 pages)
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TEST CIRCUITS AND WAVEFORMS
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
IDT49FCT806/A
FAST CMOS BUFFER/CLOCK DRIVER
O U T PU T
O U T PU T
IN P U T
G e ne rato r
N O R M A L LY
N O R M A L LY
IN P U T
P ulse
C O N TR O L
O U T P U T
O U T P U T
IN P U T
H IG H
LO W
V
IN
C L O S E D
S W IT C H
S W IT C H
t
Test Circuits for All Outputs
P L H
Enable and Disable Times
O P E N
t
E N A B LE
P L H
R
Pulse Skew - t
t
t
T
P Z L
P Z H
D .U .T .
t
t
S K
Package Delay
V
R
C C
(p ) = t
3.5 V
1.5V
1.5V
0V
V
P H L
O U T
t
-
P H Z
SK(P)
t
D IS A B L E
P LH
5 0pF
C
t
F
P H L
L
≤ 2.5ns; t
t
P L Z
t
P H L
5 0 0
50 0
0 .3 V
0 .3 V
t
F
R
Ω
Ω
≤ 2.5ns
V
V
1.5V
3V
0V
3.5V
0V
O L
O H
0.8V
2 .0 V
1.5V
V
1 .5 V
V
3V
0V
7 V
O H
O L
1 .5 V
V
1.5V
V
3 V
0V
O H
O L
6
SWITCH POSITION
DEFINITIONS:
C
R
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
L
T
P A C K A G E 2
P A C K A G E 1
= Load capacitance: includes jig and probe capacitance.
= Termination resistance: should be equal to Z
O U T P U T
O U T P U T 2
O U T P U T 1
O U T PU T
IN P U T
IN P U T
Disable HIGH
Enable HIGH
Disable LOW
Enable LOW
Test
t
S K
Part-to-Part Skew - t
t
t
(p p ) = t
P L H 1
S K
t
P L H 1
t
(o ) = t
P L H 2
t
t
P L H 2
S K (p p )
COMMERCIAL TEMPERATURE RANGE
Output Skew
t
S K (o )
P LH 2
P L H 2
-
t
-
P L H 1
t
P L H 1
OUT
o r
SK(PP)
o r
of the Pulse Generator.
t
P H L2
t
t
P H L 1
P H L2
t
t
P L H 1
P H L 2
t
Switch
Closed
t
P H L 2
S K (p p )
GND
-
t
-
P H L 1
t
S K (o )
t
P H L 1
V
V
V
V
1.5V
1.5V
1.5V
3 V
0 V
O H
O L
O H
O L
V
V
V
V
3 V
1.5V
0 V
1.5V
1.5V
O H
O L
O H
O L