IDT72V291 Integrated Device Technology, IDT72V291 Datasheet - Page 20

• Manufacturer Part Number: IDT72V291
• Description: 128k X 9 Supersync Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure. D = 65,536
5. EF goes HIGH at 60ns + 1 RCLK cycle + t
Q
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO
65,536 x 9 and 131,072 x 9
WCLK
0
for the IDT72V281 and 131,072 for the IDT72V291.
RCLK
WEN
REN
1
PAE
- Q
PAF
= first word written to the FIFO after Master Reset, W
HF
EF
RT
n
t
ENS
W
x
t
t
A
ENH
t
REF
ENS
t
RTS
.
t
RTS
Figure 11. Retransmit Timing (IDT Standard Mode)
2
= second word written to the FIFO after Master Reset.
TM
t
t
t
ENH
REF
HF
t
SKEW2
1
W
x+1
20
2
t
PAF
1
t
ENS
2
t
t
t
A
REF
PAE
COMMERCIAL AND INDUSTRIAL
(5)
W
1
TEMPERATURE RANGES
(3)
t
t
ENH
A
4513 drw 14
W
2
(3)