IDT70T3589 Integrated Device Technology, IDT70T3589 Datasheet - Page 21

• Manufacturer Part Number: IDT70T3589
• Description: 64k X 36 Sync, 3.3v/2.5v Dual-port Ram, Interleaved I/o S
• Manufacturer: Integrated Device Technology

Waveform of Collision Timing
Both Ports Writing with Left Port Clock Leading
Collision Detection Timing
NOTES:
1. CE
2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3. Leading Port Output flag might output 3t
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
NOTES:
1. CE
2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Truth Table IV — Collision Detection Flag
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
CLK
↑
↑
↑
↑
0
0 =
ADDRESS
L
Cycle Time
= V
ADDRESS
V
7.5ns
5ns
6ns
IL
IL
, CE
and CE
R/W
COL
CLK
COL
CLK
H
H
L
L
1
R
L
= V
(1)
L
(4)
R
(4)
R
L
L
1 =
IH
V
.
IH
Left Port
CE
. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
L
L
L
L
L
Region 1 (ns)
(1)
t
SA
A
0 - 2.8
0 - 3.8
0 - 5.3
0
t
SA
t
A
HA
17L
MATCH
MATCH
MATCH
MATCH
A
0
-A
t
t
CYC
OFS
HA
0L
(1)
(2)
2
t
+ t
OFS
COLS
(ns)
COL
A
after Address match.
H
L
H
L
1
Region 2 (ns)
L
3.81 - 5.6
2.81 - 4.6
5.31 - 7.1
A
(3,4)
1
CLK
(1,2)
↑
↑
↑
↑
5666 tbl 13
R
(2)
A
2
R/W
6.42
H
L
H
L
A
R
21
2
(1)
t
OFS
t
NOTES:
1. Region 1
2. Region 2
3. All the production units are tested to midpoint of each region.
4. These ranges are based on characterization of a typical device.
COLS
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.
Right Port
CE
L
L
L
L
R
(1)
A
3
A
t
COLS
A
3
t
COLR
17R
MATCH
MATCH
MATCH
MATCH
-A
Industrial and Commercial Temperature Ranges
0R
(2)
(3)
t
COL
COLR
H
H
L
L
R
Both ports reading. Not a valid collision.
No flag output on either port.
Left port reading, Right port writing.
Right port reading, Left port writing.
Both ports writing. Valid collision. Flag
output on both ports.
Valid collision, flag output on Left port.
Valid collision, flag output on Right port.
Function
5666 drw 20
APRIL 10, 2006
5666 tbl 14