IDT71V124SA Integrated Device Technology, IDT71V124SA Datasheet - Page 6

• Manufacturer Part Number: IDT71V124SA
• Description: 3.3v Cmos Static Ram 1 Meg 128k X 8-bit Center Power & Ground Pinout
• Manufacturer: Integrated Device Technology

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, t
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the t
5. Transition is measured ±200mV from steady state.
ADDRESS
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
ADDRESS
placed on the bus for the required t
DATA
DATA
DATA
OUT
WE
CS
WE
CS
IN
IN
DW
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified t
t
t
AS
AS
(3)
t
WHZ
(5)
t
t
AW
AW
WP
t
t
t
t
WC
WP
CW
WC
must be greater than or equal to t
(2)
HIGH IMPEDANCE
6
t
t
DATA
DW
DW
DATA
IN
VALID
IN
Commercial and Industrial Temperature Ranges
VALID
WHZ
t
+ t
DH
t
t
t
WR
WR
OW
DW
(3)
to allow the I/O drivers to turn off and data to be
(5)
t
DH
(3)
(1, 4)
t
(1,2,4)
CHZ
3873 drw 08
(5)
3873 drw 07
CW
write period.
WP
.
.
.