IDT7134 Integrated Device Technology, IDT7134 Datasheet - Page 10

• Manufacturer Part Number: IDT7134
• Description: High-speed 4k X 8 Dual-port Static Ram With Semaphore
• Manufacturer: Integrated Device Technology

Timing Waveform of Write Cycle No. 2, CE Controlled Timing
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
3. t
4. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
5. Timing depends on which enable signal (CE or R/W) is asserted last.
Functional Description
and I/O pins that permit independent access for reads or writes to any
location in memory. These devices have an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output Enable
control (OE). In the read mode, the port’s OE turns on the output drivers
when set LOW. Non-contention READ/WRITE conditions are illustrated
inTruth Table I.
ADDRESS
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
DATA
The IDT7134 provides two ports with separate control, address,
WR
is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.
R/W
CE
IN
EW
t
AS
or t
(5)
WP
) of a CE =V
IL
and R/W = V
t
AW
IL
.
t
EW
t
WC
(2)
10
Truth Table I – Read/Write Control
NOTE:
1. A
R/W
X
X
L
H
X
"H" = V
0L
t
- A
DW
Left or Right Port
Military, Industrial and Commercial Temperature Ranges
CE
X
11L
H
H
L
L
IH
, "L" = V
≠ A
0R
OE
X
X
X
L
H
- A
IL
, "X" = Don’t Care, and "Z" = High Impedance
11R
t
DATA
WR
DATA
(1)
D
Z
Z
Z
0-7
(3)
t
OUT
DH
IN
Port Deselected and in Power-Down
Mode, I
Mode I
Data on port written into memory
Data in memory output on port
High impedance outputs
CE
R
= CE
SB1
SB2
L
or I
= H, Power Down
or I
SB3
SB4
Function
(1,4)
2720 drw 12
2720 tbl 11