IDT72T6480 Integrated Device Technology, IDT72T6480 Datasheet - Page 30

• Manufacturer Part Number: IDT72T6480
• Description: X48 Sequential Flow-control Device Up To 1gigabit
• Manufacturer: Integrated Device Technology

AC ELECTRICAL CHARACTERISTICS
(Commercial: V
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 10ns speed grade is available as a standard device. All other speed grades are available by special order.
3. To achieve 166MHz read and write port operation, the input and/or output bus must be configured to x24 or x18.
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x12, x24, x48 BIT WIDE CONFIGURATION
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
t
t
t
t
t
t
S
A
CLK
CLKH
CLKL
DS
DH
ENS
ENH
RS
RSU
RSH
PL
RSF
OE
MC
MCYC
MCKH
MCKL
SC
SCLK
SCLKH
SCLKL
SDS
SDH
SENS
SENH
WCSS
WCSH
C1
C2
CK1
CK2
CKH1
CKH2
CKL1
CKL2
OHZ
ASO
WFFs
REFs
PAFs
PAEs
SKEW1
SKEW2
Synchronous Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
Reset Setup Time
Reset Hold Time
Reset to PLL Lock
Reset to Flag and Output
Output enable to High-Z
Output Enable Valid
Master Clock Cycle Frequency
Master Clock Cycle Time
Master Clock Cycle HIGH
Master Clock Cycle LOW
Serial Clock Cycle Frequency
Serial Clock Cycle
Serial Clock High
Serial Clock Low
Serial Data Setup
Serial Data Hold
Serial Enable Setup
Serial Enable Hold
Serial Output Data Access Time
Write Clock to Synchronous FF/IR
Read Clock to Synchronous EF/OR
WCLK to Synchronous PAF
RCLK to Synchronous PAE
Skew time between RCLK & WCLK for EF/OR and FF/IR in SDR
Skew time between RCLK and WCLK for PAE/PAF
WCS Setup Time
WCS Hold Time
Memory Clock Cycle Frequency at 166MHz
Memory Clock Cycle Frequency at 133MHz
Memory Clock Cycle Time at 166MHz
Memory Clock Cycle Time at 133MHz
Memory Clock Cycle HIGH at 166MHz
Memory Clock Cycle HIGH at 133MHz
Memory Clock Cycle LOW at 166MHz
Memory Clock Cycle LOW at 133MHz
CC
= 2.5V ± 5%, T
Parameter
A
= 0°C to +70°C;Industrial: V
CC
= 2.5V ± 5%, T
(x24 or x12 I/O width only)
(1)
Min.
29.4
0.45
0.45
0.45
0.45
0.45
0.45
100
160
128
2.7
2.7
0.5
0.5
0.5
6.2
7.8
 SYNCHRONOUS TIMING
—
10
15
10
20
—
32
—
45
45
15
—
—
—
—
—
30
1
6
2
2
1
1
5
5
5
4
5
2
A
= -40°C to +85°C)
Max.
31.3
0.55
0.55
0.55
0.55
0.55
0.55
IDT72T6480L7-5
166
170
136
5.9
7.3
—
—
—
—
—
—
—
—
—
—
—
15
34
10
—
—
—
—
—
—
—
20
—
—
—
—
4
4
4
4
4
4
4
Commercial
(3)
(x48 I/O width only)
Min.
29.4
0.45
0.45
0.45
0.45
100
160
128
7.5
3.5
3.5
2.5
0.5
2.5
0.5
2.5
0.5
7.8
—
10
15
10
20
—
32
—
45
45
15
—
—
—
—
—
—
—
—
1
1
1
5
5
5
5
7
31.3
0.55
0.55
0.55
0.55
133
170
136
Max.
7.3
—
—
—
—
—
—
—
—
—
—
—
15
34
10
—
—
—
—
—
—
—
20
—
—
—
—
—
—
—
COMMERCIAL AND INDUSTRIAL
5
5
5
5
5
5
5
TEMPERATURE RANGES
Min.
29.4
0.45
0.45
0.45
0.45
100
128
Com’l & Ind’l
IDT72T6480L10
4.5
4.5
3.5
0.5
3.5
0.5
3.5
0.5
7.8
—
10
10
15
10
20
—
32
—
45
45
15
—
—
—
—
—
10
—
—
—
—
1
1
1
5
5
5
7
OCTOBER 10, 2005
Max.
31.3
0.55
0.55
0.55
0.55
100
136
6.5
6.5
6.5
6.5
6.5
6.5
6.5
7.3
—
—
—
—
—
—
—
—
—
—
—
15
34
10
—
—
—
—
—
—
—
20
—
—
—
—
—
—
—
—
(2)
t
t
MHz
MHz
MHz
MHz
MHz
Unit
MCYC
MCYC
t
t
t
t
µs
CK1
CK2
CK1
CK2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns