IDT72T51233 Integrated Device Technology, IDT72T51233 Datasheet
IDT72T51233
Related parts for IDT72T51233
IDT72T51233 Summary of contents
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... User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL " " " " " Default multi-queue device configurations " " " " " -IDT72T51233: 8,192 -IDT72T51243: 16,384 -IDT72T51253: 32,768 100% Bus Utilization, Read and Write on every clock cycle " " " " " ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits DESCRIPTION The IDT72T51233/72T51243/72T51253 multi-queue flow-control de- vices are single chip within which anywhere between 1 and 4 discrete FIFO queues can be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port) ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WCLK WEN 5 WRADD Write Control Logic WADEN Write Pointers PAF FSTR 4 General Flag PAFn Monitor FSYNC FXO FXI Active Q FF Flags PAF SI SO Serial SCLK Multi-Queue Programming SENI ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN CONFIGURATION A1 BALL PAD CORNER A D14 D13 D12 D10 B D15 D16 D11 D9 C D17 GND GND D8 D GND GND GND V DDQ E GND GND GND V DDQ F GND GND GND ...
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... For example, depth expansion of 8 devices provides the possibility of 8 queues of 32K x 18 deep within the IDT72T51233, 64K x 18 deep within the IDT72T51243 and 128K x 18 deep within the IDT72T51253, each queue being setup within a single device utilizing all memory blocks available to produce a single queue ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS Symbol & Name I/O TYPE Pin No. D[17:0] Data Input Bus HSTL-LVTTL These are the 18 data input pins. Data is written into the device via these input pins on the rising edge ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. PAFn Flag Bus FSTR LVTTL (R4) Strobe INPUT PAFn Bus Sync FSYNC LVTTL (R3) OUTPUT PAFn Bus FXI LVTTL (T2) Expansion In INPUT PAFn Bus ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. OE Output Enable HSTL-LVTTL in High Impedance device is configured a “Slave” device, then the Qout data outputs will always be (Continued) ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. HSTL-LVTTL When enabled by REN, the rising edge of RCLK reads data from the selected queue via the output RCLK Read Clock ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. HSTL-LVTTL mode the serial data input is loaded into the first device in a chain. When that device is loaded and its SENO ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. HSTL-LVTTL next rising WCLK also, providing that WEN is LOW). Two WCLK rising edges after write queue select, WRADD Write Address ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage Temperature STG I DC Output Current OUT NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits DC ELECTRICAL CHARACTERISTICS (Commercial 2.5V ± 0.125V 0$C to +70$C;Industrial Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO (3) V Output Logic “1” Voltage Output Logic “0” Voltage, ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits HSTL 1.5V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels NOTE 1.5V±. DDQ EXTENDED HSTL 1.8V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits AC ELECTRICAL CHARACTERISTICS (Commercial 2.5V ± 0.15V 0$C to +70$C;Industrial Symbol Parameter f Clock Cycle Frequency (WCLK & RCLK Data Access Time A t Clock Cycle Time CLK t Clock High Time ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits AC ELECTRICAL CHARACTERISTICS (CONTINUED) (Commercial 2.5V ± 0.15V 0$C to +70$C;Industrial Symbol Parameter t RCLK to Echo RCLK Output ERCLK RCLK to Echo REN Output t CLKEN RCLK to PAE Flag Bus to Low-Impedance (2) t PAELZ ...
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... DF (default) pin during a master reset. For the IDT72T51233/72T51243/72T51253 devices the default mode will setup 4 queues, each queue configured as follows: For the IDT72T51233 with x9 input and x9 output ports, 16,384 one or both ports is x18, 8,192 x 18. For the IDT72T51243 with x9 input and x9 output ports, 32,768 one or both ports is x18, 16,384 x 18 ...
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... Please refer to Figure 9, Default Programming. WRITE QUEUE SELECTION & WRITE OPERATION The IDT72T51233/72T51243/72T51253 multi-queue flow-control devices have queues that data can be written into via a common write port using the data inputs, Din, write clock, WCLK and write enable, WEN. The queue ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits READ QUEUE SELECTION & READ OPERATION The multi-queue flow-control devices has queues that data is read from via a common read port using the data outputs, Qout, read clock, RCLK and read enable, REN ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits NULL QUEUE OPERATION (OF THE READ PORT) Pipelining of data to the output port enables the device to provide 100% bus utilization in standard mode. Data can be read out of the multi-queue flow-control device on every RCLK cycle regardless of queue switches or other operations. ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits OUTPUT VALID FLAG OPERATION The multi-queue flow-control devices provides a single Output Valid flag output, OV. The OV provides an empty status or data output valid status for the data word currently available on the output register of the read port. The rising ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits within a queue can be at any point within that queues depth. This location can be user programmed via the serial port or one of the default values (8 or 128) can be selected if the user has performed default programming. ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING Output Valid, OV Flag Boundary I/O Set-Up OV Goes LOW after 1 In18 to out18 or In9 to out9 (Both ports selected for same queue (see note below for timing) ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED) Programmable Almost Empty Flag, PAE Boundary I/O Set-Up In18 to out18 or In9 to out9 (Both ports selected for same queue when the 1 Word is written in until the boundary is reached) ...
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... Please refer to Figure 26, PAF n Bus – Polled Mode for timing information. PAEn FLAG BUS OPERATION The IDT72T51233/72T51243/72T51253 multi-queue flow-control de- vices can be configured for queues, each queue having its own almost empty status. An active queue has its flag status output to the discrete flags, OV and PAE, on the read port ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PAEn- POLLED BUS HIGH at Master Reset then the PAEn bus operates in Polled (Looped) mode. In polled mode the PAEn bus automatically cycles through the devices connected in expansion. In expansion mode one device will be set as the Master, MAST input tied HIGH, all other devices will have MAST tied LOW ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits ECHO READ CLOCK (ERCLK) The Echo Read Clock output is provided in both HSTL and LVTTL mode, selectable via IOSEL. The ERCLK is a free-running clock output, it will always follow the RCLK input regardless of REN and RADEN. ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT: ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits MRS t RSS WEN REN t RSS SENI t RSS FSTR, ESTR t RSS WADEN, RADEN t RSS ID0, ID1, ID2 t RSS OW RSS HIGH = Looped FM LOW = Strobed (Direct) t RSS MAST t RSS DFM ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits w-3 WCLK WADEN WEN WRADD Qx FF PAF Active Bus PAF-Qx (5) PRS RCLK REN RADEN t AS RDADD Qx OV PAE Active Bus PAE-Qx (6) r-2 NOTES: 1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports. ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 31 TEMPERATURE RANGES ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 32 TEMPERATURE RANGES ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 33 TEMPERATURE RANGES ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WCLK t ENS WEN RCLK REN Qout Last Word Read Out of Queue OV NOTES has previously been selected on both the write and read ports LOW. ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 35 TEMPERATURE RANGES ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 36 TEMPERATURE RANGES ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* *B* RCLK t ENS REN RDADD Addr=00111 RADEN Qout (Device 1) OV HIGH-Z (Device 1) OV (Device 2) WCLK WEN WRADD WADEN Din Cycle: *A* Queue 3 of Device 1 is selected for read operations. The OV is currently being driven by Device 2, a queue within device 2 is selected for reads. Device 2 also has control of Qout bus, its Qout outputs are in Low-Impedance ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 38 TEMPERATURE RANGES ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 39 TEMPERATURE RANGES ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits NULL QUEUE SELECT *A* RCLK t AS Don’t care RDADD t QS RADEN t AS Null-Q REN t A Qout Q1 Wn-4 Q1 Wn-3 OV NOTES: 1. The purpose of the Null queue operation is so that the user can stop reading a block (packet) of data from a queue without filling the 2 stage output pipeline with the next words from that queue ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* *B* WCLK WEN WRADD Addr=00110 WADEN Din PAF HIGH-Z (Device 1) PAF (Device 2) Cycle: *A* Queue 2 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance. ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* *B* RCLK REN HIGH RDADD Addr=00111 RADEN HIGH-Z Qout PAE HIGH-Z (Device 1) PAE (Device 2) Cycle: *A* Queue 3 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance. ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 43 TEMPERATURE RANGES ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* WCLK WADEN FSTR t ENS WEN WRADD D5Q3 t 100 Wp+1 Dn Writes to Previous Q RCLK RADEN ESTR REN RDADD D5Q3 100 11 Device 5 -Qn ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* *B* RCLK RADEN ESTR REN RDADD D0Q1 000 OLZ Qout W X Prev. Q WCLK t t STS STH FSTR WRADD Device ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WCLK FSYNC 0 (MASTER) FXO 0 / FXI 1 FSYNC 1 (SLAVE) FXO 1 / FXI 2 FSYNC 2 (SLAVE) FXO 2 / FXI 0 PAF[7:0] NOTE: 1. This diagram is based on 3 devices connected to expansion mode FSYNC FSYNC t t FXO ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits RCLK ESYNC 0 EXO 0 / EXI 1 ESYNC 1 EXO 1 / FXI 2 ESYNC 2 EXO 2 / EXI 0 PAE ESYNC ESYNC t t EXO EXO t ESYNC t EXO t ESYNC t EXO t t PAE PAE Device 0 Device 1 Figure 27. PAE n Bus - Polled Mode ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WCLK WEN D[39:0] D10 D11 RCLK REN Q[39: ERCLK ERCLK EREN NOTES: 1. All read and write operations must have ceased a minimum of 4 WCLK and 4 RCLK cycles before power down is asserted. ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits Serial Programming Data Input Serial Enable Data Bus Write Clock Write Enable Write Queue Select Write Address Full Strobe Programmable Almost Full Full Sync1 Full Flag Almost Full Flag ...
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... QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72T51233/72T51243/ 72T51253 incorporates the necessary tap controller and modified pad cells to implement the JTAG facility. ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits 1 0 Input = TMS NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. 2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS). ...
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... TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72T51233/72T51243/72T51253, the Part Number field con- tains the following values: Device Part# Field (HEX) ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types disabled (high-impedance) state and selects the one-bit bypass register to be connected between TDI and TDO. ...
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... IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits t 1 TCK t 3 TDI/ TMS TDO t 6 TRST t 5 SYSTEM INTERFACE PARAMETERS Parameter Symbol Test Conditions Data Output t DO (1) Data Output Hold t DOH (1) Data Input rise=3ns ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order. DATASHEET DOCUMENT HISTORY 08/05/2003 pgs. 1 through ...