IDT7005S Integrated Device Technology, IDT7005S Datasheet
IDT7005S
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IDT7005S Summary of contents
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... True Dual-Ported memory cells which allow simulta- neous access of the same memory location • High-speed access — Military: 20/25/35/55/70ns (max.) — Commercial:15/17/20/25/35/55ns (max.) • Low-power operation — IDT7005S Active: 750mW (typ.) Standby: 5mW (typ.) — IDT7005L Active: 750mW (typ.) Standby: 1mW (typ.) • ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM RAM for 16-bit-or-more word systems. Using the IDT MAS- TER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM PIN CONFIGURATIONS (CON'T 11L A 10L 12L N/C N SEM ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL (1) Inputs Outputs SEM SEM SEM SEM SEM DATA NOTE — not equal to A — ...
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... SEM — MIL 0. > 0.2V — L SEM 0.2V or 100 COM (3) = 120mA typ 6.06 MILITARY AND COMMERCIAL TEMPERATURE RANGES (V = 5.0V 10%) CC IDT7005S IDT7005L Min. Max. Min. — 10 — CC — 10 — — 0.4 — 2.4 — 2.4 ( 5.0V 10%) CC 7005X17 7005X20 Com'l. Only (2) (2) Max. ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter I Dynamic Operating CC CE Current SEM (Both Ports Active Standby Current SB1 CE (Both Ports — TTL SEM Level Inputs Standby Current SB2 CE (One Port — ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Parameter Symbol READ CYCLE t Read Cycle Time RC t Address Access Time ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM WAVEFORM OF READ CYCLES ADDR DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, 2. Timing depends on which signal is de-asserted first delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BDD has no relation to valid output data ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE Symbol Parameter WRITE CYCLE t Write Cycle Time WC t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW (3) t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM TIMING WAVEFORM OF WRITE CYCLE NO ADDRESS OE CE SEM ( DATA (4) OUT DATA IN TIMING WAVEFORM OF WRITE CYCLE NO. 2, ADDRESS CE SEM ( DATA IN NOTES must be high during all address transitions write occurs during the overlap (t ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE VALID ADDRESS t AW SEM I Write Cycle NOTES for the duration of the above timing (both write and read cycle "DATA VALID" represents all I/O's (I/O ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter BUSY TIMING ( Access Time from Address Match BAA BUSY t Disable Time from Address Not Matched BDA BUSY t Access Time from Chip Enable Low ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ WITH ADDR "A" "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING (1) ( ADDR "A" t APS ADDR " ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM WAVEFORM OF INTERRUPT TIMING ADDR "A" "A" "A" "B" INT ADDR "B" "B" OE "B" "B" INT NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM TRUTH TABLE II — ADDRESS BUSY ARBITRATION Inputs Outputs 12L BUSY BUSY BUSY BUSY BUSY ( 12R MATCH MATCH MATCH L L (2) MATCH NOTES: BUSY BUSY 1 ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM BUSY L Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs. The use of busy logic is not required or desirable for all applications. In some cases it may be useful to logically OR the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT7005 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be ...
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... IDT7005S/L HIGH-SPEED DUAL-PORT STATIC RAM ORDERING INFORMATION IDT XXXXX A 999 Device Power Speed Type A A Package Process/ Temperature Range Blank Commercial ( + 7005 6.06 MILITARY AND COMMERCIAL TEMPERATURE RANGES Military (– +125 C) ...