IDT71V124 Integrated Device Technology, IDT71V124 Datasheet - Page 5
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IDT71V124
Manufacturer Part Number
IDT71V124
Description
3.3v Cmos Static Ram 1 Meg 128k X 8-bit Revolutionary Pinout
Manufacturer
Integrated Device Technology
Datasheet
1.IDT71V124.pdf
(8 pages)
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Timing Waveform of Read Cycle No. 1
Timing Waveform of Read Cycle No. 2
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise t
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
IDT71V124, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit), Revolutionary Pinout
ADDRESS
V
DATA
CC
CURRENT
SUPPLY
ADDRESS
OUT
DATA
OUT
OE
CS
I
I
CC
SB
PREVIOUS DATA
OUT
t
PU
HIGH IMPEDANCE
VALID
t
OH
t
CLZ
t
OLZ
(5)
t
AA
(5)
t
AA
t
ACS
t
RC
6.42
(3)
5
t
RC
(1,2,4)
(1)
t
OE
AA
is the limiting parameter.
Commercial and Industrial Temperature Ranges
DATA
DATA
t
CHZ
t
PD
OUT
OUT
(5)
VALID
VALID
t
OHZ
t
OH
(5)
3484 drw 05
3484 drw 06