IDT70V3389S Integrated Device Technology, IDT70V3389S Datasheet - Page 12

• Manufacturer Part Number: IDT70V3389S
• Description: High-speed 3.3v 64k X 18 Synchronous Pipelined Dual-port Static Ram With 3.3v Or 2.5v Interface
• Manufacturer: Integrated Device Technology

NOTES:
1. CE
2. OE = V
3. If t
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE
3. Addresses do not have to be accessed sequentially since ADS = V
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
be t
port will be t
are for reference use only.
ADDRESS
ADDRESS
DATA
0
CO
0
, UB, LB, and ADS = V
, UB, LB, and ADS = V
CO
DATA
< minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will
ADDRESS
CLK
R/W
+ 2 t
CLK
R/W
IL
DATA
OUTR
DATA
for the Right Port, which is being read from. OE = V
INL
UB, LB
R
R
R
L
L
L
CYC2
CO
CLK
R/
CE
CE
OUT
+ t
W
IN
0
1
+ t
(3)
CYC
CD2
+ t
). If t
CD2
t
MATCH
t
t
SW
SD
VALID
t
t
SA
t
t
IL
IL
SB
SW
SC
SA
CO
).
; CE
; CE
MATCH
An
t
t
SW
SA
> minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite
t
t
t
t
HW
HA
HD
t
t
t
1
1
HC
HW
HA
HB
, CNTEN, and CNTRST = V
, CNTEN, and CNTRST = V
t
CH2
(1)
t
t
HW
HA
t
CYC2
t
CO
READ
(3)
t
CL2
An +1
t
CD2
IH
IH
IH
. "NOP" is "No Operation".
.
for the Left Port, which is being written to.
Qn
t
SW
An + 2
MATCH
IL
NO
constantly loads the address on the rising edge of the CLK; numbers
t
HW
6.42
NOP
12
t
CKHZ
(4)
t
t
SD
Dn + 2
CD2
An + 2
t
HD
WRITE
Industrial and Commercial Temperature Ranges
An + 3
VALID
MATCH
NO
OE
t
CKLZ
t
DC
READ
An + 4
t
CD2
Qn + 3
4832 drw 09
4832 drw 08