IDT72T51336 ETC-unknow, IDT72T51336 Datasheet - Page 50

• Manufacturer Part Number: IDT72T51336
• Description: 2.5v Multi-queue Flow-control Devices 8 Queues 36 Bit Wide Configuration 589,824 Bits, 1,179,648 Bits And 2,359,296 Bits
• Manufacturer: ETC-unknow

Device 5 PAEn
Cycle:
*A*
*AA* Q3 of Device 5 is selected for read operations.
*B*
*BB* Current Word is kept on the output bus since REN is HIGH.
*C*
*CC* Word Wa+1 of Device 5 Qp is read due to FWFT.
*D*
*DD* Word, Wy from the newly selected queue, Q3 will be read out due to FWFT operation.
*E*
*EE* Word, Wy+1 is read from Q3 of Device 5.
*F*
*FF* Word, Wy+2 is read from Q3 of Device 5.
*G*
*GG* The PAEn bus updates to show that Q3 of Device 5 is almost empty based on the reading out of word, Wy+1.
*H*
IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
Device 5 PAE
Device 5 -Qn
Prev PAEn
Bus PAEn
WRADD
WADEN
RDADD
Q3 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
A quadrant from another device has control of the PAEn bus.
The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.
Word Wp+1 is written into the previously selected queue.
Word Wp+2 is written into the previously selected queue.
Word, Wn is written into the newly selected queue, Q3 of Device 5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,
t
Device 5 is selected on the PAEn bus. Q3 of Device 5 will therefore have is PAE status output on PAE[0]. There is a single RCLK cycle latency before the PAEn bus changes
to the new selection.
Q2 of Device 3 is selected for write operations.
Word Wn+1 is written into Q3 of Device 5.
No writes occur.
The PAEn bus changes control to Device 5, the PAEn outputs of Device 5 go to Low-Impedance and quadrant 4 is placed onto the outputs. The device of the previously
selected quadrant now places its PAEn outputs into High-Impedance to prevent bus contention.
The discrete PAE flag will go HIGH to show that Q3 of Device 5 is not almost empty. Q3 of Device 5 will have its PAE status output on PAE[0].
Device 4 is selected on the write port for the PAFn bus.
The discrete PAE flag goes LOW to show that Q3 of Device 5 is almost empty based on the reading of Wy+1.
Word, Wx is written into Q2 of Device 3.
RADEN
SKEW3
WCLK
ESTR
FSTR
RCLK
REN
WEN
Dn
+ RCLK + t
RAE
t
t
ENS
QS
t
AS
(if t
t
QS
100 011
D5Q3
Previous value loaded on to PAE bus
D5 QP Status
Previous value loaded on to PAE bus
t
SKEW3
Wp
AS
*A*
Writes to Previous Q
100 011
D5Q3
*AA*
is violated one extra RCLK cycle will be added).
t
t
AH
QH
t
AH
t
t
DS
D5 QP
QH
Wa
Wp+1
*B*
1
*BB*
t
DH
Figure 28. PAE n - Direct Mode, Flag Operation
1
t
DS
Wp+2
*C*
2
*CC*
t
DH
t
2
SKEW3
t
A
t
DS
t
STS
t
AS
D5 Q3
*D*
3
50
Wn
Wa+1
101 xxx
D5 QP
Device 5
*DD*
t
DH
3
t
t
A
QS
t
AS
t
t
t
AH
t
RAE
STH
ENS
011 010
D3Q2
D5 Q3
status
Wn+1
D5Q3
*E*
Wy
D5 Q3
*EE*
t
t
AH
1
QH
t
t
ENH
A
t
PAEZL
*F*
Wy+1
D5 Q3
*FF*
t
STS
2
COMMERCIAL AND INDUSTRIAL
t
t
A
QS
t
AS
t
t
RAE
Device 4
100 xxx
PAEHZ
*G*
Device 5
Device 5
xxxx1xxx
xxxx1xxx
TEMPERATURE RANGES
Wy+2
D5 Q3
*GG*
t
t
AH
QH
t
t
3
STH
ENS
t
A
t
PAE
t
ENH
t
RAE
D3 Q2
*H*
Wx
Wy+3
D5 Q3
xxxx1xxx
Device 5
Device 5
xxxx1xxx
t
ENH
6114 drw33