SI5010 ETC, SI5010 Datasheet - Page 9

• Manufacturer Part Number: SI5010
• Description: OC-12/3 / STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC
• Manufacturer: ETC

Functional Description
The Si5010 utilizes a phase-locked loop (PLL) to
recover a clock synchronous to the input data stream.
This clock is used to retime the data, and both the
recovered clock and data are output synchronously via
current mode logic (CML) drivers. Optimal jitter
performance is obtained by using Silicon Laboratories'
DSPLL™ technology to eliminate the noise entry points
caused by external PLL loop filter components.
DSPLL
The phase-locked loop structure (shown in Figure 1 on
page 4) utilizes Silicon Laboratories' DSPLL technology
to eliminate the need for external loop filter components
found in traditional PLL implementations. This is
achieved by using a digital signal processing (DSP)
algorithm to replace the loop filter commonly found in
analog PLL designs. This algorithm processes the
phase detector error term and generates a digital
control value to adjust the frequency of the voltage
controlled oscillator (VCO). Because external loop filter
components are not required, sensitive noise entry
points are eliminated thus making the DSPLL less
susceptible to board-level noise sources that make
SONET/SDH jitter compliance difficult to attain.
PLL Self-Calibration
The Si5020 achieves optimal jitter performance by
using self-calibration circuitry to set the loop gain
parameters within the DSPLL. For the self-calibration
circuitry to operate correctly, the power supply voltage
must exceed 2.25 V when calibration occurs. For best
performance, the user should force a self-calibration
once the supply has stabilized on power-up.
A self-calibration can be initiated by forcing a
high-to-low transition on the power-down control input,
PWRDN/CAL, while a valid reference clock is supplied
to the REFCLK input. The PWRDN/CAL input should be
held high at least 1 S before transitioning low to
guarantee a self-calibration. Several application circuits
that could be used to initiate a power-on self-calibration
are provided in Silicon Laboratories application note
AN42.
Multi-Rate Operation
The Si5010 supports clock and data recovery for
OC-12/3 and STM-4/1 data streams.
Multi-rate operation is achieved by configuring the
device to divide down the output of the VCO to the
desired data rate. The RATESEL configuration and
associated data rates are given in Table 7.
™
Preliminary Rev. 0.31
Reference Clock Detect
The Si5020 uses the reference clock to center the VCO
operating frequency so that clock and data can be
recovered from the input data stream. The VCO
operates at an integer multiple of the REFCLK
frequency. (See “Lock Detect” section.) The device will
self configure for operation with one of three reference
clock frequencies. This eliminates the need to externally
configure the device to operate with a particular
reference clock. The REFCLK frequency should be
19.44 MHz,
frequency accuracy of ±100 ppm.
Lock Detect
The Si5010 provides lock-detect circuitry that indicates
whether the DSPLL has frequency locked with the
incoming data signal (DIN). The circuit compares the
frequency of a divided down version of the CLKOUT
output with the frequency of the supplied reference
clock. If the divided CLKOUT frequency deviates from
that of the reference clock by the amount specified in
Table 4 on page 7, the PLL is declared out of lock, and
the loss-of-lock (LOL) pin is asserted.
While out of lock, the DSPLL will try to reacquire lock
with the input data. During reacquisition, the clock
output
approximately 1% relative to the supplied reference
clock. The LOL output will remain asserted until the
divided clock output frequency differs from the REFCLK
frequency by less than the amount specified in Table 4.
Note: LOL is not asserted during PWRDN/CAL.
PLL Performance
The PLL implementation used in the Si5010 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 2, December 1995 and ITU-T G.958.
Jitter Tolerance
The Si5010’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 6. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
Table 7. Data-Rate Configuration
(CLKOUT)
RATESEL
77.76 MHz,
0
1
will
SONET/SDH
622.08 Mbps
155.52 Mbps
drift
or
155.52 MHz
over
Si5010
a
range
with
of
a
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