TDA1309H Philips Semiconductors, TDA1309H Datasheet - Page 7

• Manufacturer Part Number: TDA1309H
• Description: Low-voltage low-power stereo bitstream ADC/DAC
• Manufacturer: Philips Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
Figure 1 illustrates the various components of the
TDA1309H.
The analog-to-digital converter is a bitstream type
converter, both channels are sampled simultaneously.
The digital-to-analog converter is a BCC (Bitstream
Continuous Calibration) type converter. The digital filter for
the ADC is a bit serial IIR filter that produces a fairly linear
phase response up to 15 kHz. A high-pass filter is
incorporated in the down-sampling path to remove DC
offsets. An overload detection circuit is incorporated to
facilitate automatic recording level adjustment.
The digital up-sample filter for the DAC is partly IIR, with
virtual linear phase response up to 15 kHz, and partly FIR.
A switchable digital de-emphasis circuit is also
incorporated. Due to the BCC principle used, the DAC
needs only single pole post-filtering (one external
capacitor) to meet the out-of-band suppression
requirement.
The ADC and DAC channels have separate power-down
modes, to reduce power if one of them is not in use.
An analog loop-through function enables analog-input
analog-output mode without using the ADC and DAC
converters or filters, thereby switching them off to reduce
power consumption.
Table 1 Interface mode selection
Note
1. Only digital-to-analog.
Table 2 Clock edge mode
1996 Oct 21
MODE 2
Low-voltage low-power stereo bitstream
ADC/DAC
0
0
0
0
1
1
1
1
DEVICE PIN
CLKEDGE
MODE 1
0
1
0
0
1
1
0
0
1
1
MODE 0
0
1
0
1
0
1
0
1
LSB justified
LSB justified
LSB justified
LSB justified
I
I
I
I
2
2
2
2
TYPE
S-bus
S-bus
S-bus
S-bus
falling
rising
ADC
7
BITS
The digital interfaces accommodates, 16 and 18-bit,
I
can be made 3-state by means of the ADENB signal, this
enables the use of a digital bus.
The TDA1309H interface accommodates slave mode only,
therefore, the system ICs must provide the system clock,
bit clock and word clock signals. For the DAC, the
TDA1309H accepts the data together with these clocks,
for the ADC it delivers the data in response to these clocks.
Within one stereo frame, the first sample always
represents the left channel. When sending data the
unused bit positions are set to zero, when receiving data
these bit positions are don't cares.
To accommodate the various interface formats and
system clock frequencies four control pins are provided,
MODE0 to MODE2 for mode selection and CLKEDGE
which selects the active edge of the BCK signal. Table 1
gives the interface mode selection, Fig.3 illustrates the
ADC/DAC data formats and Fig.5 the operating modes.
The section of the TDA1309H is designed to
accommodate two main modes:
1. The 256f
2. The 192f
2
16
16
16
18
16
16
16
18
S-bus and LSB justified formats. The ADC digital output
digital-to-analog can be used
VALID EDGE OF BCK
ADC/DAC FORMATS
s
s
mode in which analog-to-digital and
or 384f
BCK
32f
64f
48f
64f
32f
64f
48f
64f
s
s
s
s
s
s
s
s
s
mode (digital-to-analog only).
SYS; f
256f
256f
192f
256f
256f
256f
384f
256f
falling
rising
DAC
s
s
s
s
s
s
s
s
sys
(1)
(1)
Product specification
TDA1309H
FIGURE
3(a)
3(b)
4(a)
3(c)
3(d)
3(e)
4(b)
3(f)