TDA1312 Philips Semiconductors, TDA1312 Datasheet - Page 5

• Manufacturer Part Number: TDA1312
• Description: Stereo continuous calibration DAC CC-DAC
• Manufacturer: Philips Semiconductors

Philips Semiconductors
PINNING
FUNCTIONAL DESCRIPTION
The basic operation of the continuous calibration DAC is
illustrated in Fig.3. The figure shows the calibration and
operation cycle. During calibration of the MOS current
source (Fig.3a) transistor M1 is connected as a diode by
applying a reference current. The voltage V
intrinsic gate-source capacitance C
determined by the transistor characteristics. After
calibration of the drain current to the reference value I
the switch S1 is opened and S2 is switched to the other
position (Fig.3b). The gate-to-source voltage V
not changed because the charge on C
Therefore, the drain current of M1 will still be equal to I
and this exact duplicate of I
terminal.
The 32 current sources and the spare current source of the
TDA1312A; AT are continuously calibrated (see Fig.1).
The spare current source is included to allow continuous
converter operation. The output of one calibrated source is
July 1993
BCK
DATAR
DATAL
GND
V
V
V
WS
DD
OL
OR
Stereo continuous calibration
DAC (CC-DAC)
SYMBOL
PIN
1
2
3
4
5
6
7
8
REF
bit clock input
right data input
left data input
ground
positive supply voltage
left channel output
right channel output
word select input
is now available at the OUT
DESCRIPTION
gs
of M1 is then
gs
is preserved.
gs
on the
gs
of M1 is
ref
REF
,
5
connected to an 11-bit binary current divider consisting of
2048 transistors. A symmetrical offset decoding principle
is incorporated and arranges the bit switching in such a
way that the zero-crossing is performed only by switching
the LSB currents.
The TDA1312A; AT (CC-DAC) accepts serial input data
formats of 16-bit word length. Left and right data words are
time multiplexed. The most significant bit (bit 1) must
always be first. The input data format is shown in Figs.4
and 5.
Data is placed in the right and left input registers (see
Fig.1). The data in the input registers is simultaneously
latched in the output registers which control the bit
switches.
An internal offset voltage V
output voltage V
Where V
handbook, halfpage
DD1
/V
DATAR
DATAL
GND
DD2
BCK
FS
Fig.2 Pin configuration.
TDA1312A; TDA1312AT
= V
; V
1
2
3
4
OFF
FS1
TDA1312AT
TDA1312
/V
and V
OFF
FS2
MGE224
= V
FS
is added to the full scale
Preliminary specification
are proportional to V
OFF1
7
6
5
8
/V
WS
V OL
V DD
V OR
OFF2
.
DD
: