TDA1548T Philips Semiconductors, TDA1548T Datasheet - Page 6

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TDA1548T

Manufacturer Part Number
TDA1548T
Description
Bitstream continuous calibration filter-DAC with headphone driver and DSP
Manufacturer
Philips Semiconductors
Datasheet

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Philips Semiconductors
FUNCTIONAL DESCRIPTION
The TDA1548T CMOS DAC incorporates an up-sampling
digital filter, a linear interpolator, a noise shaper,
continuous calibrated current sources and headphone
amplifiers. The 1f
oversampling rate of 64f
together with the 5-bit DAC, enables the filtering required
for waveform smoothing and out-of-band noise reduction
to be achieved by simple first-order analog post-filtering.
System clock and data input format
The TDA1548T accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable at pins CLSEL, MODE0 and MODE1
(see Table 1).
The TDA1548T supports the following data input modes
(see Table 2):
The input formats are illustrated in Fig.4. Left and right
data-channel words are time multiplexed.
Analog control of digital sound processing features
Digital sound processing settings are controlled via analog
sense inputs that translate an analog voltage from, for
example, a potentiometer wiper to a digital code, which is
then further translated internally to a set of coefficients for
either treble, bass boost or volume.
The analog input value is acquired by an internal 6-bit
ADC, sampling the three input pins ADVC, ADBB and
ADTR and the three-mode selection pin ADS3 (see
Section “Single pin three mode selection”) in a multiplexed
fashion. Sampling of the input voltage is performed by a
straight forward technique of linear approximation; from
the starting value of 0 V, an internal linear approximation
voltage is incremented periodically in steps of 1/66th of the
scale, with an internal comparator detecting when the
approximation value oversteps the input value. Tolerance
is built in at the top and bottom end of the scale by
dimensioning the resistive elements at the top and bottom
of the ladder equals 1R. Thus the ladder is built up of
64 elements of value R, two of value R, making a typical
quantization step size of approximately 1.5 V (AD
divided-by-66 (amount of Rs), equals 22.7 mV.
1995 Nov 15
I
LSB justified serial format with data word length of 16,
18 or 20 bits.
Bitstream continuous calibration filter-DAC
with headphone driver and DSP
2
S-bus with data word length of up to 20 bits
s
input data is increased to an
s
. This high-rate oversampling,
ref
)
6
For each multiplexed timeslot the full approximation cycle
is completed, immediately after which the next input will
start being sampled.
The time slot for one input lasts 64 steps at a step advance
rate of 8
Because four inputs are multiplexed, the sample rate for
each analog input is 1.38 kHz.
A buffered version of an internally generated reference
voltage is available at output pin AD
internal AD derives from the same reference voltage, this
allows for optimum mapping of the external analog control
value onto the useful AD input voltage range. The idea is
to bias a potentiometer to AD
the input voltage between 0 V and AD
implemented to improve noise immunity of the AD in order
to prevent a stable setting of the potentiometer, to a point
near a quantization threshold, from producing two
alternating digital codes which could give rise to audible
volume or boost changes. An hysteresis of 1 LSB is
implemented digital. A shift in code must be at least 2 LSB
either up or down from the current value, otherwise the
internal digital code will remain at the current value.
S
A special input pin AD3S (pin 22), controls the mode in
which the sound processing block operates. Not between
two but three modes; whether the DSP should follow the
AD inputs applying maximum effect, the minimum effect or
overrule the boost effects thereby resulting in a flat
frequency characteristic in the treble and bass boost
sections.
Internally the same AD is used to detect the input level
present at this pin as is used for the three sound control
pins. An internal bias circuit containing of two MOSTs
supplies a mid-range voltage so that this input can be
operated with a minimum of external components. A HIGH
or LOW input level is created by tying the pin to AD
ground respectively, the intermediate value is achieved by
leaving the pin open-circuit.
Volume control
Since there is no headroom included into the sound control
section, the volume control precedes the sound control.
Full volume and neutral setting (flat) of the sound control
results in a full-scale output. Any tone boost will
immediately cause clipping, which can be avoided by
reducing the volume setting.
INGLE PIN THREE MODE SELECTION
f
s
, which amounts to 181 s at f
ref
, using a wiper to control
ref
Product specification
. Because the
ref
TDA1548T
. Hysteresis is
s
= 44.1 kHz.
ref
or

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