MCP3302-XI/SL Microchip Technology, MCP3302-XI/SL Datasheet - Page 17

• Manufacturer Part Number: MCP3302-XI/SL
• Description: 13-Bit Differential Input, Low Power A/D Converter with SPI Serial Interface, -40C to +85C, 14-SOIC 150mil, TUBE
• Manufacturer: Microchip Technology

6.0
6.1
The MCP3302/04 A/D converters employ a conven-
tional SAR architecture. With this architecture, the
potential between the IN+ and IN- inputs are
simultaneously sampled and stored with the internal
sample circuits for 1.5 clock cycles. Following this
sampling time, the input hold switches of the converter
open and the device uses the collected charge to
produce a serial 13-bit binary two’s complement output
code. This conversion process is driven by the external
clock and must include 13 clock cycles, one for each
bit. During this process, the most significant bit (MSB)
is output first. This bit is the sign bit and indicates if the
IN+ or IN- input is at a higher potential.
FIGURE 6-1:
© 2007 Microchip Technology Inc.
IN+
IN-
Hold
Hold
APPLICATIONS INFORMATION
Conversion Description
C
C
SAMP
SAMP
Simplified Block Diagram.
+
-
Comp
CDAC
D
13-Bit SAR
Register
OUT
Shift
6.2
The analog input of the MCP3302/04 is easily driven,
either differentially or single ended. Any signal that is
common to the two input channels will be rejected by
the common mode rejection of the device. During the
charging time of the sample capacitor, a small charging
current will be required. For low source impedances,
this input can be driven directly. For larger source
impedances, a larger acquisition time will be required
due to the RC time constant that includes the source
impedance.
specification, the charge holding capacitor (C
must be given enough time to acquire a 13-bit accurate
voltage level during the 1.5 clock cycle acquisition
period.
An analog input model is shown in
model is accurate for an analog input, regardless if it is
configured as a single ended input, or the IN+ and IN-
input in differential mode. In this diagram, it is shown
that the source impedance (R
sampling switch (R
time that is required to charge the capacitor (C
Consequently, a larger source impedance with no
additional acquisition time increases the offset, gain
and integral linearity errors of the conversion. To over-
come this, a slower clock speed can be used to allow
for the longer charging time.
maximum clock speed associated with source imped-
ances.
FIGURE 6-2:
vs. Source Resistance (R
INL.
2.5
2.0
1.5
1.0
0.5
0.0
100
Driving the Analog Input
For
SS
Source Resistance (ohms)
the
1000
) impedance, directly affecting the
MCP3302/04
Maximum Clock Frequency
A/D
S
) to maintain ±1 LSB
S
Figure 6-2
) adds to the internal
Converter
10000
DS21697D-page 17
Figure
shows the
to
6-3. This
SAMPLE
SAMPLE
100000
meet
).
)