MCP3421 Microchip Technology, MCP3421 Datasheet - Page 17

• Manufacturer Part Number: MCP3421
• Description: 18-Bit Analog-to-Digital Converter with I2C Interface and On-Board Reference
• Manufacturer: Microchip Technology

5.5
The I
device must be ‘activated’ to operate in high-speed
mode. This is done by sending a special address byte
of 00001XXX following the START bit. The XXX bits are
unique to the High-Speed (HS) mode Master. This byte
is referred to as the High-Speed (HS) Master Mode
Code (HSMMC). The MCP3421 device does not
acknowledge this byte. However, upon receiving this
code, the MCP3421 switches on its HS mode filters
and communicates up to 3.4 MHz on SDA and SCL.
The device will switch out of the HS mode on the next
STOP condition.
For more information on the HS mode, or other I
modes, please refer to the Phillips I
5.6
The I
protocol:
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined using
5.6.1
Both data and clock lines remain HIGH.
5.6.2
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
5.6.3
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations can be ended with a STOP condition.
FIGURE 5-6:
© 2006 Microchip Technology Inc.
SDA
SCL
is not busy.
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
2
C specification requires that a high-speed mode
2
C specification defines the following bus
(A)
High-Speed (HS) Mode
I
2
C Bus Characteristics
BUS NOT BUSY (A)
START DATA TRANSFER (B)
STOP DATA TRANSFER (C)
Figure
CONDITION
START
(B)
5-6.
Data Transfer Sequence on the Serial Bus.
2
C specification.
ACKNOWLEDGE
ADDRESS OR
VALID
(D)
2
C
TO CHANGE
ALLOWED
DATA
5.6.4
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition.
5.6.5
The Master (microcontroller) and the slave (MCP3421)
use an acknowledge pulse as a hand shake of
communication for each byte. The ninth clock pulse of
each byte is used for the acknowledgement. The
acknowledgement is achieved by pulling-down the
SDA line “LOW” during the 9th clock pulse. The clock
pulse is always provided by the Master (microcontrol-
ler) and the acknowledgement is issued by the
receiving device of the byte (Note: The transmitting
device must release the SDA line (“HIGH”) during the
acknowledge
(MCP3421) issues the acknowledgement (bring down
the SDA line “LOW”) after the end of each receiving
byte, and the master (microcontroller) issues the
acknowledgement when it reads data from the Slave
(MCP3421).
When the MCP3421 is addressed, it generates an
acknowledge after receiving each byte successfully.
The Master device (microcontroller) must provide an
extra clock pulse (9th pulse of each byte) for the
acknowledgement from the MCP3421 (slave).
The MCP3421 (slave) pulls-down the SDA line during
the acknowledge clock pulse in such a way that the
SDA line is stable low during the high period of the
acknowledge clock pulse.
During reads, the Master (microcontroller) can
terminate the current read operation by not providing
an acknowledge bit on the last byte that has been
clocked out from the MCP3421. In this case, the
MCP3421 releases the SDA line to allow the master
(microcontroller) to generate a STOP or repeated
START condition.
DATA VALID (D)
ACKNOWLEDGE
(D)
pulse.).
For
MCP3421
example,
DS22003B-page 17
CONDITION
the
STOP
(C)
slave
(A)