TDA8415 Philips Semiconductors, TDA8415 Datasheet - Page 8

• Manufacturer Part Number: TDA8415
• Description: TV and VTR stereo/dual sound processor with integrated filters and I2C-bus control
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Control ports
The general purpose control ports C1 and C2 can be set to LOW, HIGH or high impedance via the I
I
Bus specification
The TDA8415 is controlled, via the bidirectional 2-line I
(SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer
may be initiated only when the bus is not busy.
When the bus is free both lines are HIGH. The data on the SDA line must be stable during the HIGH period of the clock.
The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The set up and
hold times are specified in the CHARACTERISTICS.
A HIGH-to-LOW transition of the SDA line while SCL is HIGH is defined as the start condition (S). A LOW-to-HIGH
transition of the SDA line while SCL is HIGH is defined as the stop condition (P). The bus receiver will be reset on the
reception of a start condition. The bus is considered to be busy after the start condition. The bus is considered to be free
again after a stop condition.
The I
The TDA8415 is controlled by a microcomputer and can be written to or read from via the I
The first byte is the address and determines whether the TDA8415 is to be read from (status register) or written to (switch
register or mute and port control register).
May 1989
2
C-bus receiver and data handling
TV and VTR stereo/dual sound processor
with integrated filters and I
Where S = start bit and A = acknowledge bit
2
C-BUS PROTOCOL OF THE TDA8415
2
C-bus control
Fig.4 Address byte.
2
C-bus, by a microcomputer. The two lines are a serial data line
8
2
C-bus.
Preliminary specification
2
C-bus.
TDA8415