TDA9847 Philips Semiconductors, TDA9847 Datasheet - Page 8

• Manufacturer Part Number: TDA9847
• Description: TV and VTR stereo/dual sound processor with digital identification
• Manufacturer: Philips Semiconductors

Philips Semiconductors
When the microcontroller has only open drain ports
available for the C1, C2 and C3 control line, external
pull-up resistors must be connected to these control lines.
Figure 7 shows an example of a timing diagram to program
the main and SCART register of the TDA9847 with a
microcontroller via the control lines C1, C2, C3 and C4.
Both registers are programmed with the same control line
levels: C1 = LOW, C2 = HIGH and C3 = LOW. The dual
identification frequency is detected and the dual LED is
switched-on. The A-signal (dual mode) is fed to all
AF outputs (see Tables 1 and 2). This is shown in the
beginning of this timing diagram.
The second period of time shows the programming of the
external mode (C3 goes to HIGH: CC-signal) for the main
channel. The switch positions are immediately changed to
the external AF source, because the C4 level is LOW. The
dual LED is switched-off by the logic (see Section
“External mode”).
The next periods of time show the way to change the
switch positions for the SCART channel to route B-signals
to the AF outputs (dual mode: BB). At first the control
output Port of the microcontroller for the C4 line goes into
the high ohmic state. The changing of the C1, C2 or C3
level has no influence on the register data. In the timing
diagram the C1 level changes from LOW-to-HIGH and the
C3 level goes from HIGH-to-LOW. In the next steps the C4
line goes from 3-state-to-HIGH, and the level of the other
control lines are valid for the SCART channel, and the
B-signals are fed (dual mode: BB) to the AF outputs of the
main channel.
After some time in this example the C1 and C2 levels
change from HIGH-to-LOW and the C3 level goes from
LOW-to-HIGH (sound mute). The SCART channel is
immediately muted, because the level of the C4 line is
HIGH.
The last period of time shows the programming of the dual
mode (AA) for the main channel. At first the control output
Port of the microcontroller for the C4 line goes into the high
ohmic state. The changing of the C1, C2 or C3 level has
no influence on the register data. The switch positions of
the SCART channel stay in the sound mute.
In the 3-state mode the C2 level changes from
LOW-to-HIGH, and the C3 level goes from HIGH-to-LOW.
When the C4 level is LOW, the level of the other control
lines are valid for the main channel. The A-signal (dual
mode) is fed to the main outputs.
The operation mode mute (see Table 1) can be achieved
from any position of the C4 control line without going via
3-state.
1995 May 23
TV and VTR stereo/dual sound processor
with digital identification
8
Figure 5 shows the hold and set-up time of the C1,
C2 and C3 control line in the 3-state mode,
see Chapter “Characteristics”.
M
Figure 11 shows an example of an application circuit for
TDA9847 (V
microcontroller, which has open drain output ports to
control the main and SCART channel. Four resistors and
two output ports of the microcontroller are necessary to
generate the 3-state voltage. The other control lines have
a pull-up resistor (10 k ) in the event of open drain output
stages. These resistors are not necessary for LOW/HIGH
output ports of the microcontroller having internal pull-up
or push-pull stages. The values and tolerances of these
components are given in this figure. Table 4 shows the
conversion logic truth table.
For information about programming the different operation
mode selections see Section “Operating mode selection”.
Power supply
The different supply voltages and currents required for the
analog and digital circuits are derived from an internal
band-gap reference circuit. The AF reference voltage is
1
is added. A good ripple rejection is achieved with the
external capacitor C
the high ohmic input of the
DC load on this pin is allowed.
Power-On Reset (POR)
When a POR is activated by switching on the supply
voltage or because of a supply voltage breakdown, the
117/274 Hz DPLL, the 117/274 Hz integrator and the logic
will be reset. Both AF channels (main and SCART) are
muted ( 1 ms).
ESD protection
All pins are ESD protected. The protection circuits
represent the latest state of the art.
Internal circuit
The internal pin configuration is given in Fig.7.
2
ICROCONTROLLER WITH
V
P
. For a fast setting to
P
= 4.5 to 8.8 V) in conjunction with a
ref
= 100 F/16 V in conjunction with
LOW/HIGH
1
1
2
V
2
V
P
P
an internal start-up circuit
pin (pin 8). No additional
Preliminary specification
OUTPUT PORTS
TDA9847