MCP6546-ILT Microchip Technology, MCP6546-ILT Datasheet - Page 13

• Manufacturer Part Number: MCP6546-ILT
• Description: Open-Drain Output Sub-Microamp Comparators
• Manufacturer: Microchip Technology

FIGURE 3-4:
inverting circuit.
The trip points for Figures 3-3 and 3-4 are given by:
EQUATION
The output current required to drive V
EQUATION
As explained in Section 3.2, it is important to keep the
non-inverting input below V
3.4
The MCP6548 is a single comparator with a chip select
(CS) option. When CS is pulled high, the total current
consumption drops to 20 pA (typ). 1 pA (typ) flows
through the CS pin, 1 pA (typ) flows through the output
pin and 18 pA (typ) flows through the V
shown in Figure 1-1. When this happens, the compar-
ator output is put into a high-impedance state. By pull-
ing CS low, the comparator is enabled. If the CS pin is
left floating, the comparator will not operate properly.
Figure 1-1 shows the output voltage and supply current
response to a CS pulse.
V
THL
2002 Microchip Technology Inc.
V
V
V
V
PU
OL
SS
H
V
=
V
SS
TLH
V
The MCP6548 Chip Select (CS)
Option
V
Low-to-High
PU
OUT
I
O
=
V
------------------------------------- -
R
=
H
V
23
V
V
--------------------------
O L
REF
=
+
PU
R
R
R
V
---------------------
R
R
V
–
PU
23
F
PU
23
23
TLH
=
Hysteresis diagram for the
+
R
V
+
23
OL
V
R
=
------------------------------------- -
R
R
D D
PU
V
23
R
+
DD
F
THL
R
2
+
V
---------------------------- -
23
------------------
R
+0.3V when V
+
+
R
REF
R
2
R
High-to-Low
+
V
V
F
23
R
3
+
REF
REF
3
R
+
+
R
–
F
R
3
R
V
PU
OL
F
OL
------------------------------------- -
R
---------------------
R
23
23
is:
R
R
V
+
+
DD
F
F
DD
R
R
PU
+
F
F
R
+
pin, as
> V
PU
V
R
IN
PU
DD
.
The internal CS circuitry is designed to minimize
glitches when cycling the CS pin. This helps conserve
power, which is especially important in battery-powered
applications.
3.5
The open-drain output is designed to make level-shift-
ing and wired-OR logic easy to implement. The output
can go as high as 10V for 9V battery-powered applica-
tions. The output stage minimizes switching current
(shoot-through current from supply-to-supply) when
the output changes state. See Figures 2-15, 2-17, 2-32
through 2-36 for more information.
3.6
Reasonable capacitive loads (e.g., logic gates) have lit-
tle impact on propagation delay (see Figure 2-27). The
supply current increases with increasing toggle fre-
quency (Figure 2-30), especially with higher capacitive
loads.
3.7
In order to maximize battery life in portable applica-
tions, use large resistors and small capacitive loads.
Also, avoid toggling the output more than necessary,
and do not use chip select (CS) to conserve power for
short periods of time. Capacitive loads will draw
additional power at start-up.
3.8
Good PC board layout techniques will help you achieve
the performance shown in the specs and Typical Per-
formance Curves. It will also help you minimize EMC
(Electro-Magnetic Compatibility) issues.
3.8.1
In applications where low input bias current is critical,
PC board surface leakage effects and signal coupling
from trace-to-trace need to be considered.
Surface leakage is caused by a difference in voltage
between traces, combined with high humidity, dust or
other contamination on the board. Under low humidity
conditions, a typical resistance between nearby traces
is 10
to flow, which is greater than the input current of the
The simplest technique to reduce surface leakage is
using a guard ring around sensitive pins (or traces).
The guard ring is biased at the same voltage as the
sensitive pin or trace. Figure 3-5 shows an example of
a typical layout.
family at 25°C (1 pA, typ).
12
W. A 5V difference would cause 5 pA of current
Open-Drain Output
Capacitive Loads
Battery Life
Layout Considerations
SURFACE LEAKAGE
MCP6546/7/8/9
DS21714B-page 13