NCP1575 ON Semiconductor, NCP1575 Datasheet - Page 14

• Manufacturer Part Number: NCP1575
• Description: Low Voltage Synchronous Buck Controller
• Manufacturer: ON Semiconductor

minus I
to the output ripple current, we can approximate the input
capacitor current waveform as a square wave. We can then
calculate the RMS input capacitor ripple current:
worst case input ripple current. This will require several
capacitors in parallel. In addition to the worst case current,
attention must be paid to the capacitor manufacturer’s
derating for operation over temperature.
5 V to 3.3 V conversion at 10 A at an ambient temperature
of 60 C. Efficiency of 80% is assumed. Average input
current in the input filter inductor is:
current rating for a 6.3 V, 1800 nF capacitor is 2000 mA at
100 kHz and 105 C. We determine the number of input
capacitors by dividing the ripple current by the
per−capacitor current rating:
meet the input capacitor ripple current requirements.
Output Switch FETs
properties vary widely from manufacturer to manufacturer.
The NCP1575 system is designed assuming that n−channel
FETs will be used. The FET characteristics of most concern
are the gate charge/gate−source threshold voltage, gate
capacitance, on−resistance, current rating and the thermal
capability of the package.
the switch FET has a high gate charge, the amount of time
the FET stays in its ohmic region during the turn−on and
turn−off transitions is larger than that of a low gate charge
FET, with the result that the high gate charge FET will
consume more power. Similarly, a low on−resistance FET
will dissipate less power than will a higher on−resistance
I RMS(CIN) +
I IN(RMS) +
The input capacitance must be designed to conduct the
As an example, let us define the input capacitance for a
Input capacitor RMS ripple current is then
If we consider a Rubycon MBZ series capacitor, the ripple
A total of at least 3 capacitors in parallel must be used to
Output switch FETs must be chosen carefully, since their
The onboard FET driver has a limited drive capability. If
Number of capacitors + 4.74 A 2.0 A + 2.3
IN(AVE)
I IN(AVE) + (10 A)(3.3 V 5 V) + 6.6 A
+ 4.74 A
. If we ignore the small current variation due
6.6 2 ) 3.3 V
I
2
IN(AVE)
[( 10 A * 6.6 A ) 2 * 6.6 A 2 ]
I OUT per phase * I IN(AVE) 2 * I
)
5 V
V OUT
V IN
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2
IN(AVE)
NCP1575
14
FET at a given current. Thus, low gate charge and low
R
generated heat.
reduce power consumption. By placing a number of FETs in
parallel, the effective R
ohmic power loss. However, placing FETs in parallel
increases the gate capacitance so that switching losses
increase. As long as adding another parallel FET reduces the
ohmic power loss more than the switching losses increase,
there is some advantage to doing so. However, at some point
the law of diminishing returns will take hold, and a marginal
increase in efficiency may not be worth the board area
required to add the extra FET. Additionally, as more FETs
are used, the limited drive capability of the FET driver will
have to charge a larger gate capacitance, resulting in
increased gate voltage rise and fall times. This will affect the
amount of time the FET operates in its ohmic region and will
increase power dissipation.
dissipation in the switch FETs.
practice to use the value of R
junction temperature in the calculations shown above.
where:
where:
P ON(BOTTOM) +
DS(ON)
I RMS(BOTTOM) + I
It can be advantageous to use multiple switch FETs to
The following equations can be used to calculate power
For ohmic power losses due to R
Note that R
D = Duty cycle.
For switching power losses:
n = number of switch FETs (either top or bottom),
C = FET gate capacitance,
V = maximum gate drive voltage (usually V
f
OSC
I RMS(TOP) +
P ON(TOP) +
I PEAK + I LOAD )
= switching frequency.
will result in higher efficiency and will reduce
I RIPPLE +
DS(ON)
P D + nCV 2 (f OSC )
R DS(ON)(BOTTOM) I RMS(BOTTOM) 2
( R DS(ON)(TOP) )( I RMS(TOP) ) 2
increases with temperature. It is good
2
PK
I
2
PK
DS(ON)
( number of topside FETs )
* (I PK I RIPPLE ) )
(V IN * V OUT )(V OUT )
number of bottom−side FETs
I RIPPLE
* (I PK )(I RIPPLE ) ) D
(f OSC )(L)(V IN )
2
DS(ON)
is reduced, thus reducing the
+
DS(ON)
at the FET’s maximum
I OUT
3
)
:
(1 * D)
I RIPPLE
3
3
CC
I
2
2
RIPPLE
),
I
2
RIPPLE