NCP5393 ON Semiconductor, NCP5393 Datasheet
NCP5393
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NCP5393 Summary of contents
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... NCP5393 2/3/4-Phase Controller for CPU Applications The NCP5393 controls up to four V phase to provide a buck regulator solution for current and next-generation AMD processors. The NCP5393 incorporates differential voltage sensing, differential phase current sensing, optional load-line voltage positioning, and programmable V V offsets to provide accurately regulated power parallel- and DDNB serial-VID AMD processors ...
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... NCP5393 48 1 VCCA GND COMP FB DROOP VS+ VS- OFFSET DIFFOUT VFIX 12VMON PSI_L Figure 1. Pinout http://onsemi.com 2 VID1 VID0 NB_COMP NB_FB NB_DROOP NB_VS+ NB_VS- NB_OFFSET NB_DIFFOUT ROSC VID5 VID4 ...
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... PMW3 Gain = PWM4 Gain = 6 VDD Oscillator + ILIMIT_VDD - + - 5V UVLO 4.25V/4.05V VDD_SRL VDD_DAC + - 12V UVLO NCP5393 8.5V/7.5V Figure 2. NCP5393 Block Diagram http://onsemi.com 3 + NB_G - HI-Z MID OVP FAULT VDD PSI_L NB_DRVON NB REGULATOR Fault Logic and Monitor Circuits NB OFFSET SCALING X NB_OFFSET NB_DAC OUT PWRGOOD + NB PWROK ...
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... Figure 3. NCP5393 Configured for Phases, with Optional Droop NCP5393 http://onsemi.com 4 ...
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... NB_VS- 31 NB_VS+ NCP5393 Description 5 V supply pin for the NCP5393. The V bypassing capacitance must be connected between this CC pin and GND (preferably returned to the package flag). Small-signal power supply return. This pin should be tied directly to the package flag (exposed pad). Output of the voltage error amplifier for the V ...
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... NCP5393 PIN DESCRIPTIONS Pin No. Symbol 32 NB_DROOP 33 NB_FB 34 NB_COMP 35 VID0 36 VID1 37 PWROK 38 ENABLE 39 VID3/SVC 40 VID2/SVD 41 PWRGOOD 42 NB_DRVON 43 DRVON 44 NB_G www.DataSheet4U.com FLAG PGND PIN CONNECTIONS VS. PHASE COUNT Number of Phases G4 4 Phase 4 Out 3 Tie to GND 2 Tie to GND NCP5393 Voltage output signal proportional to total current drawn from the VDDNB regulator. Used when load line operation (“ ...
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... Operating Junction Temperature Range (Note 2) Operating Ambient Temperature Range Maximum Storage Temperature Range Moisture Sensitivity Level, QFN Package * The maximum package power dissipation must be observed. 1. JESD 51-5 (1S2P Direct-Attach Method) with 0 LFM. 2. JESD 51-7 (1S2P Direct-Attach Method) with 0 LFM. NCP5393 V MAX 13.2 V 7.0 V 5.5 V 5 ...
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... Droop Amplifier Output Droop Amplifier DC Output Voltage Slew Rate Maximum Output Voltage Minimum Output Voltage Output Source Current (Note 3) Output Sink Current (Note 3) 3. Guaranteed by design. Not production tested. NCP5393 v70°C; 4.75 VvV (Unless otherwise stated: 0°CvT A Test Conditions & DDNB ...
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... Magnitude of the PWM Ramp 0% Duty Cycle 100% Duty Cycle PWM Phase Angle Error PWRGOOD OUTPUT PWRGOOD Output Voltage (Low) PWRGOOD Rise Time PWRGOOD High-State Leakage 3. Guaranteed by design. Not production tested. NCP5393 v70°C; 4.75 VvV (Unless otherwise stated: 0°CvT A Test Conditions & DDNB CSx = CSxN = 1 ...
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... Enable Input Pull-Up Current VFIXEN INPUT (Active-Low Input) VFIXEN Input Voltage (High) VFIXEN Input Voltage (Low) VFIXEN Hysteresis VFIXEN Input Pull-Up Current 3. Guaranteed by design. Not production tested. NCP5393 v70°C; 4.75 VvV (Unless otherwise stated: 0°CvT A Test Conditions V Increasing, DAC = 1.3 V (Wrt DAC) ...
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... VCCA UVLO Start Threshold VCCA UVLO Stop Threshold VCCA UVLO Hysteresis INPUT SUPPLY CURRENT VCC Operating Current 12VMON 12VMON (High Threshold) 12VMON (Low Threshold) 12VMON Hysteresis 3. Guaranteed by design. Not production tested. NCP5393 (Unless otherwise stated: 0°CvT A Test Conditions V HIGH V LOW ...
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... T , JUNCTION TEMPERATURE (°C) J Figure 4.5 V Increasing Voltage CCP 4.0 V Decreasing Voltage CCP 3.5 3 JUNCTION TEMPERATURE (°C) J Figure 5. V CCP Threshold Voltage vs. Temperature NCP5393 TYPICAL CHARACTERISTICS 1.5 1.4 1.3 1.2 1.1 1 231.1 230.8 230.5 230.2 229.9 229.6 229.3 229 Current vs. Temperature 2.009 2.008 2.007 2 ...
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... AMD processors. Dual-edge multiphase modulation provides the fastest initial response to dynamic load events. NCP5393 is able to detect which kind of CPU is connected in order to configure itself to work as a Single-Plane PVI controller or Dual-Plane SVI controller. The NCP5393 manages On the Fly VID transitions and maintains the slew rates as defined when the transitions take place ...
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... VDDNB oscillator will free-run at a frequency which is nominally 1.25 ratio of f CPU Support NCP5393 is able to detect the CPU it is going to supply and configure itself accordingly. At system Start-up, on the rising-edge of the EN signal, the device monitors the status of VID1 and switches in PVI mode (VID1 = 1) or SVI mode (VID1 = 0) ...
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... SVI - Serial Interface SVI is a two wire, Clock and Data, bus that connects a single master (AMD processor) to one NCP5393. The master initiates and terminates SVI transactions and drives the clock, SVC, and the data SVD, during a transaction. The slave receives the SVI transactions and acts accordingly. ...
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... NCP5393 (V) SVID[6:0] V (V) SVID[6:0] OUT 010_0000 1.1500 100_0000 010_0001 1.1375 100_0001 010_0010 1.1250 100_0010 010_0011 1.1125 100_0011 010_0100 1.1000 100_0100 010_0101 1 ...
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... Start-up sequences are presented below: • Boot VID is captured from SVC and SVD pins on rising edge of ENABLE. NCP5393 • This capture is INDEPENDENT of any other signal. SVI/PVI is determined by sampling VID[1] during rising edge of ENABLE (SVI: VID[1]=0, PVI: VID[1]=1). Once SVI/PVI is determined, the VID controller is enabled and increments to the Boot VID at the Soft Start rate ...
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... Pre-PWROK Metal VID. In PVI mode, VID[0:5] or V_FIX VID in V_FIX mode are the set output voltages. Typical soft start sequence timing in SVI mode is given in Figure 12. Figure 12. Soft-Start Sequence to Vcore = 1.3 V http://onsemi.com 18 voltage is removed and CC The NCP5393 simply ramps V to boot voltage at a core to the final core ...
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... Selecting the closest available values of 16.9 kW for RLIM1 and 13.7 kW for RLIM2 yield a nominal operating frequency of 330 kHz and an approximate current NCP5393 proportional to the resistance and frequency is inversely proportional to the total resistance. The total resistance may be estimated by Equation 2. This equation is valid for the individual phase frequency in both three and four phase mode ...
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... The reference for this ADC is VCC. The ADC's output is ratiometric to VCC. Voffset IN represents the voltage applied to the OFFSET or NB_OFFSET pin intended that these voltages be derived by a resistive divider from Vcc. The recommended total driving impedance is <10 kilohms. NCP5393 to GND. Output offsets are ratiometric Offset = 0 ...
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... L 48X e/2 BOTTOM VIEW The products described herein (NCP5393), may be covered by one or more of the following U.S. patents, pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “ ...